nuvoton,wpcm450-pinctrl.yaml

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    1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Nuvoton WPCM450 pin control and GPIO
    8 
    9 maintainers:
   10   - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
   11 
   12 properties:
   13   compatible:
   14     const: nuvoton,wpcm450-pinctrl
   15 
   16   reg:
   17     maxItems: 1
   18 
   19   '#address-cells':
   20     const: 1
   21 
   22   '#size-cells':
   23     const: 0
   24 
   25 patternProperties:
   26   # There are three kinds of subnodes:
   27   # 1. a GPIO controller node for each GPIO bank
   28   # 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2)
   29   # 3. a pinconf node configures properties of a single pin
   30 
   31   "^gpio@[0-7]$":
   32     type: object
   33 
   34     description:
   35       Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18
   36       GPIOs. Some GPIOs support interrupts.
   37 
   38     properties:
   39       reg:
   40         minimum: 0
   41         maximum: 7
   42 
   43       gpio-controller: true
   44 
   45       "#gpio-cells":
   46         const: 2
   47 
   48       interrupt-controller: true
   49 
   50       "#interrupt-cells":
   51         const: 2
   52 
   53       interrupts:
   54         maxItems: 3
   55         description:
   56           The interrupts associated with this GPIO bank
   57 
   58     required:
   59       - reg
   60       - gpio-controller
   61       - '#gpio-cells'
   62 
   63   "^mux-":
   64     $ref: pinmux-node.yaml#
   65 
   66     properties:
   67       groups:
   68         description:
   69           One or more groups of pins to mux to a certain function
   70         items:
   71           enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
   72                   hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo,
   73                   clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0,
   74                   fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11,
   75                   fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
   76                   pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ]
   77       function:
   78         description:
   79           The function that a group of pins is muxed to
   80         enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
   81                 hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0,
   82                 dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc,
   83                 gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4,
   84                 fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15,
   85                 pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1,
   86                 hg2, hg3, hg4, hg5, hg6, hg7, gpio ]
   87 
   88     dependencies:
   89       groups: [ function ]
   90       function: [ groups ]
   91 
   92     additionalProperties: false
   93 
   94   "^cfg-":
   95     $ref: pincfg-node.yaml#
   96 
   97     properties:
   98       pins:
   99         description:
  100           A list of pins to configure in certain ways, such as enabling
  101           debouncing
  102         items:
  103           pattern: "^gpio1?[0-9]{1,2}$"
  104 
  105       input-debounce: true
  106 
  107     additionalProperties: false
  108 
  109 required:
  110   - compatible
  111   - reg
  112 
  113 additionalProperties: false
  114 
  115 examples:
  116   - |
  117     #include <dt-bindings/interrupt-controller/irq.h>
  118     #include <dt-bindings/gpio/gpio.h>
  119     pinctrl: pinctrl@b8003000 {
  120       compatible = "nuvoton,wpcm450-pinctrl";
  121       reg = <0xb8003000 0x1000>;
  122       #address-cells = <1>;
  123       #size-cells = <0>;
  124 
  125       gpio0: gpio@0 {
  126         reg = <0>;
  127         gpio-controller;
  128         #gpio-cells = <2>;
  129         interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
  130                      <3 IRQ_TYPE_LEVEL_HIGH>,
  131                      <4 IRQ_TYPE_LEVEL_HIGH>;
  132       };
  133 
  134       mux-rmii2 {
  135         groups = "rmii2";
  136         function = "rmii2";
  137       };
  138 
  139       pinmux_uid: mux-uid {
  140         groups = "gspi", "sspi";
  141         function = "gpio";
  142       };
  143 
  144       pinctrl_uid: cfg-uid {
  145         pins = "gpio14";
  146         input-debounce = <1>;
  147       };
  148     };
  149 
  150     gpio-keys {
  151       compatible = "gpio-keys";
  152       pinctrl-names = "default";
  153       pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>;
  154 
  155       button-uid {
  156         label = "UID";
  157         linux,code = <102>;
  158         gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
  159       };
  160     };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml