qcom,msm8998-pinctrl.txt

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    1 Qualcomm MSM8998 TLMM block
    2 
    3 This binding describes the Top Level Mode Multiplexer block found in the
    4 MSM8998 platform.
    5 
    6 - compatible:
    7         Usage: required
    8         Value type: <string>
    9         Definition: must be "qcom,msm8998-pinctrl"
   10 
   11 - reg:
   12         Usage: required
   13         Value type: <prop-encoded-array>
   14         Definition: the base address and size of the TLMM register space.
   15 
   16 - interrupts:
   17         Usage: required
   18         Value type: <prop-encoded-array>
   19         Definition: should specify the TLMM summary IRQ.
   20 
   21 - interrupt-controller:
   22         Usage: required
   23         Value type: <none>
   24         Definition: identifies this node as an interrupt controller
   25 
   26 - #interrupt-cells:
   27         Usage: required
   28         Value type: <u32>
   29         Definition: must be 2. Specifying the pin number and flags, as defined
   30                     in <dt-bindings/interrupt-controller/irq.h>
   31 
   32 - gpio-controller:
   33         Usage: required
   34         Value type: <none>
   35         Definition: identifies this node as a gpio controller
   36 
   37 - #gpio-cells:
   38         Usage: required
   39         Value type: <u32>
   40         Definition: must be 2. Specifying the pin number and flags, as defined
   41                     in <dt-bindings/gpio/gpio.h>
   42 
   43 - gpio-ranges:
   44         Usage: required
   45         Definition:  see ../gpio/gpio.txt
   46 
   47 - gpio-reserved-ranges:
   48         Usage: optional
   49         Definition: see ../gpio/gpio.txt
   50 
   51 Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
   52 a general description of GPIO and interrupt bindings.
   53 
   54 Please refer to pinctrl-bindings.txt in this directory for details of the
   55 common pinctrl bindings used by client devices, including the meaning of the
   56 phrase "pin configuration node".
   57 
   58 The pin configuration nodes act as a container for an arbitrary number of
   59 subnodes. Each of these subnodes represents some desired configuration for a
   60 pin, a group, or a list of pins or groups. This configuration can include the
   61 mux function to select on those pin(s)/group(s), and various pin configuration
   62 parameters, such as pull-up, drive strength, etc.
   63 
   64 
   65 PIN CONFIGURATION NODES:
   66 
   67 The name of each subnode is not important; all subnodes should be enumerated
   68 and processed purely based on their content.
   69 
   70 Each subnode only affects those parameters that are explicitly listed. In
   71 other words, a subnode that lists a mux function but no pin configuration
   72 parameters implies no information about any pin configuration parameters.
   73 Similarly, a pin subnode that describes a pullup parameter implies no
   74 information about e.g. the mux function.
   75 
   76 
   77 The following generic properties as defined in pinctrl-bindings.txt are valid
   78 to specify in a pin configuration subnode:
   79 
   80 - pins:
   81         Usage: required
   82         Value type: <string-array>
   83         Definition: List of gpio pins affected by the properties specified in
   84                     this subnode.
   85 
   86                     Valid pins are:
   87                       gpio0-gpio149
   88                         Supports mux, bias and drive-strength
   89 
   90                       sdc2_clk, sdc2_cmd, sdc2_data
   91                         Supports bias and drive-strength
   92 
   93                       ufs_reset
   94                         Supports bias and drive-strength
   95 
   96 - function:
   97         Usage: required
   98         Value type: <string>
   99         Definition: Specify the alternative function to be configured for the
  100                     specified pins. Functions are only valid for gpio pins.
  101                     Valid values are:
  102 
  103                     gpio, adsp_ext, agera_pll, atest_char, atest_gpsadc0,
  104                     atest_gpsadc1, atest_tsens, atest_tsens2, atest_usb1,
  105                     atest_usb10, atest_usb11, atest_usb12, atest_usb13,
  106                     audio_ref, bimc_dte0, bimc_dte1, blsp10_spi, blsp10_spi_a,
  107                     blsp10_spi_b, blsp11_i2c, blsp1_spi, blsp1_spi_a,
  108                     blsp1_spi_b, blsp2_spi, blsp9_spi, blsp_i2c1, blsp_i2c2,
  109                     blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7,
  110                     blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
  111                     blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
  112                     blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
  113                     blsp_spi11, blsp_spi12, blsp_uart1_a, blsp_uart1_b,
  114                     blsp_uart2_a, blsp_uart2_b, blsp_uart3_a, blsp_uart3_b,
  115                     blsp_uart7_a, blsp_uart7_b, blsp_uart8, blsp_uart8_a,
  116                     blsp_uart8_b, blsp_uart9_a, blsp_uart9_b, blsp_uim1_a,
  117                     blsp_uim1_b, blsp_uim2_a, blsp_uim2_b, blsp_uim3_a,
  118                     blsp_uim3_b, blsp_uim7_a, blsp_uim7_b, blsp_uim8_a,
  119                     blsp_uim8_b, blsp_uim9_a, blsp_uim9_b, bt_reset,
  120                     btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
  121                     cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
  122                     cri_trng0, cri_trng1, dbg_out, ddr_bist, edp_hot, edp_lcd,
  123                     gcc_gp1_a, gcc_gp1_b, gcc_gp2_a, gcc_gp2_b, gcc_gp3_a,
  124                     gcc_gp3_b, hdmi_cec, hdmi_ddc, hdmi_hot, hdmi_rcv,
  125                     isense_dbg, jitter_bist, ldo_en, ldo_update, lpass_slimbus,
  126                     m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
  127                     mdp_vsync3, mdp_vsync_a, mdp_vsync_b, modem_tsync, mss_lte,
  128                     nav_dr, nav_pps, pa_indicator, pci_e0, phase_flag,
  129                     pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc,
  130                     pwr_crypto, pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b,
  131                     qdss_cti1_a, qdss_cti1_b, qdss, qlink_enable,
  132                     qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41,
  133                     sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu,
  134                     spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1,
  135                     tsense_pwm1, tsense_pwm2, tsif0, tsif1,
  136                     uim1_clk, uim1_data, uim1_present,
  137                     uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
  138                     uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0,
  139                     vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1,
  140                     wlan2_adc0, wlan2_adc1,
  141 
  142 - bias-disable:
  143         Usage: optional
  144         Value type: <none>
  145         Definition: The specified pins should be configured as no pull.
  146 
  147 - bias-pull-down:
  148         Usage: optional
  149         Value type: <none>
  150         Definition: The specified pins should be configured as pull down.
  151 
  152 - bias-pull-up:
  153         Usage: optional
  154         Value type: <none>
  155         Definition: The specified pins should be configured as pull up.
  156 
  157 - output-high:
  158         Usage: optional
  159         Value type: <none>
  160         Definition: The specified pins are configured in output mode, driven
  161                     high.
  162                     Not valid for sdc pins.
  163 
  164 - output-low:
  165         Usage: optional
  166         Value type: <none>
  167         Definition: The specified pins are configured in output mode, driven
  168                     low.
  169                     Not valid for sdc pins.
  170 
  171 - drive-strength:
  172         Usage: optional
  173         Value type: <u32>
  174         Definition: Selects the drive strength for the specified pins, in mA.
  175                     Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
  176 
  177 Example:
  178 
  179         tlmm: pinctrl@03400000 {
  180                 compatible = "qcom,msm8998-pinctrl";
  181                 reg = <0x03400000 0xc00000>;
  182                 interrupts = <0 208 0>;
  183                 gpio-controller;
  184                 #gpio-cells = <2>;
  185                 gpio-ranges = <&tlmm 0 0 175>;
  186                 gpio-reserved-ranges = <0 4>, <81 4>;
  187                 interrupt-controller;
  188                 #interrupt-cells = <2>;
  189 
  190                 uart_console_active: uart_console_active {
  191                         mux {
  192                                 pins = "gpio4", "gpio5";
  193                                 function = "blsp_uart8_a";
  194                         };
  195 
  196                         config {
  197                                 pins = "gpio4", "gpio5";
  198                                 drive-strength = <2>;
  199                                 bias-disable;
  200                         };
  201                 };
  202         };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/pinctrl/qcom,msm8998-pinctrl.txt

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sys/contrib/device-tree/Bindings/pinctrl/qcom,msm8998-pinctrl.txt