qcom,sm6375-tlmm.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6375-tlmm.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Qualcomm Technologies, Inc. SM6375 TLMM block
    8 
    9 maintainers:
   10   - Konrad Dybcio <konrad.dybcio@somainline.org>
   11 
   12 description: |
   13   This binding describes the Top Level Mode Multiplexer (TLMM) block found
   14   in the SM6375 platform.
   15 
   16 allOf:
   17   - $ref: "pinctrl.yaml#"
   18   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
   19 
   20 properties:
   21   compatible:
   22     const: qcom,sm6375-tlmm
   23 
   24   reg:
   25     maxItems: 1
   26 
   27   interrupts: true
   28   interrupt-controller: true
   29   '#interrupt-cells': true
   30   gpio-controller: true
   31   gpio-reserved-ranges: true
   32   '#gpio-cells': true
   33   gpio-ranges: true
   34   wakeup-parent: true
   35 
   36 required:
   37   - compatible
   38   - reg
   39 
   40 additionalProperties: false
   41 
   42 patternProperties:
   43   '-state$':
   44     oneOf:
   45       - $ref: "#/$defs/qcom-sm6375-tlmm-state"
   46       - patternProperties:
   47           ".*":
   48             $ref: "#/$defs/qcom-sm6375-tlmm-state"
   49 
   50 $defs:
   51   qcom-sm6375-tlmm-state:
   52     type: object
   53     description:
   54       Pinctrl node's client devices use subnodes for desired pin configuration.
   55       Client device subnodes use below standard properties.
   56     $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
   57 
   58     properties:
   59       pins:
   60         description:
   61           List of gpio pins affected by the properties specified in this
   62           subnode.
   63         items:
   64           oneOf:
   65             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$"
   66             - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
   67                       sdc2_cmd, sdc2_data ]
   68         minItems: 1
   69         maxItems: 36
   70 
   71       function:
   72         description:
   73           Specify the alternative function to be configured for the specified
   74           pins.
   75 
   76         enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
   77                 atest_char2, atest_char3, atest_tsens, atest_tsens2,
   78                 atest_usb1, atest_usb10, atest_usb11, atest_usb12,
   79                 atest_usb13, atest_usb2, atest_usb20, atest_usb21,
   80                 atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
   81                 cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
   82                 cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist,
   83                 ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd,
   84                 gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio,
   85                 gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext,
   86                 m_voc, mclk, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
   87                 mdp_vsync3, mi2s_0, mi2s_1, mi2s_2, mss_lte, nav_gpio,
   88                 nav_pps, pa_indicator, phase_flag0, phase_flag1, phase_flag10,
   89                 phase_flag11, phase_flag12, phase_flag13, phase_flag14,
   90                 phase_flag15, phase_flag16, phase_flag17, phase_flag18,
   91                 phase_flag19, phase_flag2, phase_flag20, phase_flag21,
   92                 phase_flag22, phase_flag23, phase_flag24, phase_flag25,
   93                 phase_flag26, phase_flag27, phase_flag28, phase_flag29,
   94                 phase_flag3, phase_flag30, phase_flag31, phase_flag4,
   95                 phase_flag5, phase_flag6, phase_flag7, phase_flag8,
   96                 phase_flag9, pll_bist, pll_bypassnl, pll_clk, pll_reset,
   97                 prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
   98                 qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11,
   99                 qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15,
  100                 qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
  101                 qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable,
  102                 qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
  103                 qlink1_wmss, qup00, qup01, qup02, qup10, qup11_f1, qup11_f2,
  104                 qup12, qup13_f1, qup13_f2, qup14, sd_write, sdc1_tb, sdc2_tb,
  105                 sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
  106                 tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset,
  107                 uim2_clk, uim2_data, uim2_present, uim2_reset, usb2phy_ac,
  108                 usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
  109                 wlan2_adc0, wlan2_adc1 ]
  110 
  111 
  112       bias-disable: true
  113       bias-pull-down: true
  114       bias-pull-up: true
  115       drive-strength: true
  116       input-enable: true
  117       output-high: true
  118       output-low: true
  119 
  120     required:
  121       - pins
  122       - function
  123 
  124     additionalProperties: false
  125 
  126 examples:
  127   - |
  128         #include <dt-bindings/interrupt-controller/arm-gic.h>
  129         pinctrl@500000 {
  130                 compatible = "qcom,sm6375-tlmm";
  131                 reg = <0x00500000 0x800000>;
  132                 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
  133                 gpio-controller;
  134                 #gpio-cells = <2>;
  135                 interrupt-controller;
  136                 #interrupt-cells = <2>;
  137                 gpio-ranges = <&tlmm 0 0 157>;
  138 
  139                 gpio-wo-subnode-state {
  140                         pins = "gpio1";
  141                         function = "gpio";
  142                 };
  143 
  144                 uart-w-subnodes-state {
  145                         rx {
  146                                 pins = "gpio18";
  147                                 function = "qup13_f2";
  148                                 bias-pull-up;
  149                         };
  150 
  151                         tx {
  152                                 pins = "gpio19";
  153                                 function = "qup13_f2";
  154                                 bias-disable;
  155                         };
  156                 };
  157         };
  158 ...

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/pinctrl/qcom,sm6375-tlmm.yaml

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/pinctrl/qcom,sm6375-tlmm.yaml