qcom,sm8150-pinctrl.txt

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    1 Qualcomm SM8150 TLMM block
    2 
    3 This binding describes the Top Level Mode Multiplexer block found in the
    4 QCS404 platform.
    5 
    6 - compatible:
    7         Usage: required
    8         Value type: <string>
    9         Definition: must be "qcom,sm8150-pinctrl"
   10 
   11 - reg:
   12         Usage: required
   13         Value type: <prop-encoded-array>
   14         Definition: the base address and size of the north, south, west
   15                     and east TLMM tiles.
   16 
   17 - reg-names:
   18         Usage: required
   19         Value type: <prop-encoded-array>
   20         Defintiion: names for the cells of reg, must contain "north", "south"
   21                     "west" and "east".
   22 
   23 - interrupts:
   24         Usage: required
   25         Value type: <prop-encoded-array>
   26         Definition: should specify the TLMM summary IRQ.
   27 
   28 - interrupt-controller:
   29         Usage: required
   30         Value type: <none>
   31         Definition: identifies this node as an interrupt controller
   32 
   33 - #interrupt-cells:
   34         Usage: required
   35         Value type: <u32>
   36         Definition: must be 2. Specifying the pin number and flags, as defined
   37                     in <dt-bindings/interrupt-controller/irq.h>
   38 
   39 - gpio-controller:
   40         Usage: required
   41         Value type: <none>
   42         Definition: identifies this node as a gpio controller
   43 
   44 - #gpio-cells:
   45         Usage: required
   46         Value type: <u32>
   47         Definition: must be 2. Specifying the pin number and flags, as defined
   48                     in <dt-bindings/gpio/gpio.h>
   49 
   50 - gpio-ranges:
   51         Usage: required
   52         Value type: <prop-encoded-array>
   53         Definition:  see ../gpio/gpio.txt
   54 
   55 - gpio-reserved-ranges:
   56         Usage: optional
   57         Value type: <prop-encoded-array>
   58         Definition: see ../gpio/gpio.txt
   59 
   60 Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
   61 a general description of GPIO and interrupt bindings.
   62 
   63 Please refer to pinctrl-bindings.txt in this directory for details of the
   64 common pinctrl bindings used by client devices, including the meaning of the
   65 phrase "pin configuration node".
   66 
   67 The pin configuration nodes act as a container for an arbitrary number of
   68 subnodes. Each of these subnodes represents some desired configuration for a
   69 pin, a group, or a list of pins or groups. This configuration can include the
   70 mux function to select on those pin(s)/group(s), and various pin configuration
   71 parameters, such as pull-up, drive strength, etc.
   72 
   73 
   74 PIN CONFIGURATION NODES:
   75 
   76 The name of each subnode is not important; all subnodes should be enumerated
   77 and processed purely based on their content.
   78 
   79 Each subnode only affects those parameters that are explicitly listed. In
   80 other words, a subnode that lists a mux function but no pin configuration
   81 parameters implies no information about any pin configuration parameters.
   82 Similarly, a pin subnode that describes a pullup parameter implies no
   83 information about e.g. the mux function.
   84 
   85 
   86 The following generic properties as defined in pinctrl-bindings.txt are valid
   87 to specify in a pin configuration subnode:
   88 
   89 - pins:
   90         Usage: required
   91         Value type: <string-array>
   92         Definition: List of gpio pins affected by the properties specified in
   93                     this subnode.
   94 
   95                     Valid pins are:
   96                       gpio0-gpio149
   97                         Supports mux, bias and drive-strength
   98 
   99                       sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
  100                       sdc2_data sdc1_rclk
  101                         Supports bias and drive-strength
  102 
  103                       ufs_reset
  104                         Supports bias and drive-strength
  105 
  106 - function:
  107         Usage: required
  108         Value type: <string>
  109         Definition: Specify the alternative function to be configured for the
  110                     specified pins. Functions are only valid for gpio pins.
  111                     Valid values are:
  112 
  113                     adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
  114                     atest_char0, atest_char1, atest_char2, atest_char3,
  115                     audio_ref, atest_usb1, atest_usb2, atest_usb10,
  116                     atest_usb11, atest_usb12, atest_usb13, atest_usb20,
  117                     atest_usb21, atest_usb22, atest_usb2, atest_usb23,
  118                     btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
  119                     cci_timer1, cci_timer2, cci_timer3, cci_timer4,
  120                     cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
  121                     ddr_pxi0, ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd,
  122                     emac_phy, emac_pps, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
  123                     hs1_mi2s, hs2_mi2s, hs3_mi2s, jitter_bist,
  124                     lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
  125                     mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps,
  126                     pa_indicator, pci_e0, phase_flag, pll_bypassnl,
  127                     pll_bist, pci_e1, pll_reset, pri_mi2s, pri_mi2s_ws,
  128                     prng_rosc, qdss, qdss_cti, qlink_request, qlink_enable,
  129                     qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qua_mi2s,
  130                     qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
  131                     qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16,
  132                     qup17, qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii,
  133                     sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu, ter_mi2s,
  134                     tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
  135                     tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
  136                     usb2phy_ac, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
  137                     wlan1_adc1, wlan2_adc0, wlan2_adc1, wmss_reset
  138 
  139 - bias-disable:
  140         Usage: optional
  141         Value type: <none>
  142         Definition: The specified pins should be configued as no pull.
  143 
  144 - bias-pull-down:
  145         Usage: optional
  146         Value type: <none>
  147         Definition: The specified pins should be configued as pull down.
  148 
  149 - bias-pull-up:
  150         Usage: optional
  151         Value type: <none>
  152         Definition: The specified pins should be configued as pull up.
  153 
  154 - output-high:
  155         Usage: optional
  156         Value type: <none>
  157         Definition: The specified pins are configured in output mode, driven
  158                     high.
  159                     Not valid for sdc pins.
  160 
  161 - output-low:
  162         Usage: optional
  163         Value type: <none>
  164         Definition: The specified pins are configured in output mode, driven
  165                     low.
  166                     Not valid for sdc pins.
  167 
  168 - drive-strength:
  169         Usage: optional
  170         Value type: <u32>
  171         Definition: Selects the drive strength for the specified pins, in mA.
  172                     Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
  173 
  174 Example:
  175 
  176         tlmm: pinctrl@3000000 {
  177                 compatible = "qcom,sm8150-pinctrl";
  178                 reg = <0x03100000 0x300000>,
  179                       <0x03500000 0x300000>,
  180                       <0x03900000 0x300000>,
  181                       <0x03D00000 0x300000>;
  182                 reg-names = "west", "east", "north", "south";
  183                 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
  184                 gpio-controller;
  185                 #gpio-cells = <2>;
  186                 gpio-ranges = <&tlmm 0 0 175>;
  187                 gpio-reserved-ranges = <0 4>, <126 4>;
  188                 interrupt-controller;
  189                 #interrupt-cells = <2>;
  190         };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/pinctrl/qcom,sm8150-pinctrl.txt

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/pinctrl/qcom,sm8150-pinctrl.txt