renesas,rzg2l-pinctrl.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
    8 
    9 maintainers:
   10   - Geert Uytterhoeven <geert+renesas@glider.be>
   11   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
   12 
   13 description:
   14   The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
   15   GPIO controller.
   16   Pin multiplexing and GPIO configuration is performed on a per-pin basis.
   17   Each port features up to 8 pins, each of them configurable for GPIO function
   18   (port mode) or in alternate function mode.
   19   Up to 8 different alternate function modes exist for each single pin.
   20 
   21 properties:
   22   compatible:
   23     oneOf:
   24       - items:
   25           - enum:
   26               - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}
   27               - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
   28 
   29       - items:
   30           - enum:
   31               - renesas,r9a07g054-pinctrl     # RZ/V2L
   32           - const: renesas,r9a07g044-pinctrl  # RZ/G2{L,LC} fallback for RZ/V2L
   33 
   34   reg:
   35     maxItems: 1
   36 
   37   gpio-controller: true
   38 
   39   '#gpio-cells':
   40     const: 2
   41     description:
   42       The first cell contains the global GPIO port index, constructed using the
   43       RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
   44       second cell represents consumer flag as mentioned in ../gpio/gpio.txt
   45       E.g. "RZG2L_GPIO(39, 1)" for P39_1.
   46 
   47   gpio-ranges:
   48     maxItems: 1
   49 
   50   interrupt-controller: true
   51 
   52   '#interrupt-cells':
   53     const: 2
   54     description:
   55       The first cell contains the global GPIO port index, constructed using the
   56       RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
   57       second cell is used to specify the flag.
   58       E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is
   59       being used as an interrupt.
   60 
   61   clocks:
   62     maxItems: 1
   63 
   64   power-domains:
   65     maxItems: 1
   66 
   67   resets:
   68     items:
   69       - description: GPIO_RSTN signal
   70       - description: GPIO_PORT_RESETN signal
   71       - description: GPIO_SPARE_RESETN signal
   72 
   73 additionalProperties:
   74   anyOf:
   75     - type: object
   76       allOf:
   77         - $ref: pincfg-node.yaml#
   78         - $ref: pinmux-node.yaml#
   79 
   80       description:
   81         Pin controller client devices use pin configuration subnodes (children
   82         and grandchildren) for desired pin configuration.
   83         Client device subnodes use below standard properties.
   84 
   85       properties:
   86         phandle: true
   87         pinmux:
   88           description:
   89             Values are constructed from GPIO port number, pin number, and
   90             alternate function configuration number using the RZG2L_PORT_PINMUX()
   91             helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
   92         pins: true
   93         drive-strength:
   94           enum: [ 2, 4, 8, 12 ]
   95         output-impedance-ohms:
   96           enum: [ 33, 50, 66, 100 ]
   97         power-source:
   98           description: I/O voltage in millivolt.
   99           enum: [ 1800, 2500, 3300 ]
  100         slew-rate: true
  101         gpio-hog: true
  102         gpios: true
  103         input-enable: true
  104         output-high: true
  105         output-low: true
  106         line-name: true
  107 
  108     - type: object
  109       properties:
  110         phandle: true
  111 
  112       additionalProperties:
  113         $ref: "#/additionalProperties/anyOf/0"
  114 
  115 allOf:
  116   - $ref: "pinctrl.yaml#"
  117 
  118 required:
  119   - compatible
  120   - reg
  121   - gpio-controller
  122   - '#gpio-cells'
  123   - gpio-ranges
  124   - interrupt-controller
  125   - '#interrupt-cells'
  126   - clocks
  127   - power-domains
  128   - resets
  129 
  130 examples:
  131   - |
  132     #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
  133     #include <dt-bindings/clock/r9a07g044-cpg.h>
  134 
  135     pinctrl: pinctrl@11030000 {
  136             compatible = "renesas,r9a07g044-pinctrl";
  137             reg = <0x11030000 0x10000>;
  138 
  139             gpio-controller;
  140             #gpio-cells = <2>;
  141             gpio-ranges = <&pinctrl 0 0 392>;
  142             interrupt-controller;
  143             #interrupt-cells = <2>;
  144             clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
  145             resets = <&cpg R9A07G044_GPIO_RSTN>,
  146                      <&cpg R9A07G044_GPIO_PORT_RESETN>,
  147                      <&cpg R9A07G044_GPIO_SPARE_RESETN>;
  148             power-domains = <&cpg>;
  149 
  150             scif0_pins: serial0 {
  151                     pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
  152                              <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
  153             };
  154 
  155             i2c1_pins: i2c1 {
  156                     pins = "RIIC1_SDA", "RIIC1_SCL";
  157                     input-enable;
  158             };
  159 
  160             sd1-pwr-en-hog {
  161                     gpio-hog;
  162                     gpios = <RZG2L_GPIO(39, 2) 0>;
  163                     output-high;
  164                     line-name = "sd1_pwr_en";
  165             };
  166 
  167             sdhi1_pins: sd1 {
  168                     sd1_mux {
  169                             pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
  170                                      <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
  171                             power-source  = <3300>;
  172                     };
  173 
  174                     sd1_data {
  175                             pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
  176                             power-source  = <3300>;
  177                     };
  178 
  179                     sd1_ctrl {
  180                             pins = "SD1_CLK", "SD1_CMD";
  181                             power-source  = <3300>;
  182                     };
  183             };
  184     };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

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sys/contrib/device-tree/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml