renesas,rzn1-pinctrl.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Renesas RZ/N1 Pin Controller
    8 
    9 maintainers:
   10   - Gareth Williams <gareth.williams.jx@renesas.com>
   11   - Geert Uytterhoeven <geert+renesas@glider.be>
   12 
   13 properties:
   14   compatible:
   15     items:
   16       - enum:
   17           - renesas,r9a06g032-pinctrl # RZ/N1D
   18           - renesas,r9a06g033-pinctrl # RZ/N1S
   19       - const: renesas,rzn1-pinctrl   # Generic RZ/N1
   20 
   21   reg:
   22     items:
   23       - description: GPIO Multiplexing Level1 Register Block
   24       - description: GPIO Multiplexing Level2 Register Block
   25 
   26   clocks:
   27     maxItems: 1
   28 
   29   clock-names:
   30     const: bus
   31     description:
   32       The bus clock, sometimes described as pclk, for register accesses.
   33 
   34 allOf:
   35   - $ref: "pinctrl.yaml#"
   36 
   37 required:
   38   - compatible
   39   - reg
   40   - clocks
   41   - clock-names
   42 
   43 additionalProperties:
   44   anyOf:
   45     - type: object
   46       allOf:
   47         - $ref: pincfg-node.yaml#
   48         - $ref: pinmux-node.yaml#
   49 
   50       description:
   51         A pin multiplexing sub-node describes how to configure a set of (or a
   52         single) pin in some desired alternate function mode.
   53         A single sub-node may define several pin configurations.
   54 
   55       properties:
   56         pinmux:
   57           description: |
   58             Integer array representing pin number and pin multiplexing
   59             configuration.
   60             When a pin has to be configured in alternate function mode, use
   61             this property to identify the pin by its global index, and provide
   62             its alternate function configuration number along with it.
   63             When multiple pins are required to be configured as part of the
   64             same alternate function they shall be specified as members of the
   65             same argument list of a single "pinmux" property.
   66             Integers values in the "pinmux" argument list are assembled as:
   67             (PIN | MUX_FUNC << 8)
   68             where PIN directly corresponds to the pl_gpio pin number and
   69             MUX_FUNC is one of the alternate function identifiers defined in:
   70             <include/dt-bindings/pinctrl/rzn1-pinctrl.h>
   71             These identifiers collapse the IO Multiplex Configuration Level 1
   72             and Level 2 numbers that are detailed in the hardware reference
   73             manual into a single number. The identifiers for Level 2 are simply
   74             offset by 10.  Additional identifiers are provided to specify the
   75             MDIO source peripheral.
   76 
   77         phandle: true
   78         bias-disable: true
   79         bias-pull-up:
   80           description: Pull up the pin with 50 kOhm
   81         bias-pull-down:
   82           description: Pull down the pin with 50 kOhm
   83         bias-high-impedance: true
   84         drive-strength:
   85           enum: [ 4, 6, 8, 12 ]
   86 
   87       required:
   88         - pinmux
   89 
   90       additionalProperties:
   91         $ref: "#/additionalProperties/anyOf/0"
   92 
   93     - type: object
   94       properties:
   95         phandle: true
   96 
   97       additionalProperties:
   98         $ref: "#/additionalProperties/anyOf/0"
   99 
  100 examples:
  101   - |
  102     #include <dt-bindings/clock/r9a06g032-sysctrl.h>
  103     #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
  104     pinctrl: pinctrl@40067000 {
  105             compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
  106             reg = <0x40067000 0x1000>, <0x51000000 0x480>;
  107             clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
  108             clock-names = "bus";
  109 
  110             /*
  111              * A serial communication interface with a TX output pin and an RX
  112              * input pin.
  113              */
  114             pins_uart0: pins_uart0 {
  115                     pinmux = <
  116                             RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
  117                             RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
  118                     >;
  119             };
  120 
  121             /*
  122              * Set the pull-up on the RXD pin of the UART.
  123              */
  124             pins_uart0_alt: pins_uart0_alt {
  125                     pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>;
  126 
  127                     pins_uart6_rx {
  128                             pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>;
  129                             bias-pull-up;
  130                     };
  131             };
  132     };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/pinctrl/renesas,rzn1-pinctrl.yaml

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/pinctrl/renesas,rzn1-pinctrl.yaml