qcom,cpr.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/power/avs/qcom,cpr.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Qualcomm Core Power Reduction (CPR) bindings
    8 
    9 maintainers:
   10   - Niklas Cassel <nks@flawful.org>
   11 
   12 description: |
   13   CPR (Core Power Reduction) is a technology to reduce core power on a CPU
   14   or other device. Each OPP of a device corresponds to a "corner" that has
   15   a range of valid voltages for a particular frequency. While the device is
   16   running at a particular frequency, CPR monitors dynamic factors such as
   17   temperature, etc. and suggests adjustments to the voltage to save power
   18   and meet silicon characteristic requirements.
   19 
   20 properties:
   21   compatible:
   22     items:
   23       - enum:
   24           - qcom,qcs404-cpr
   25       - const: qcom,cpr
   26 
   27   reg:
   28     description: Base address and size of the RBCPR register region.
   29     maxItems: 1
   30 
   31   interrupts:
   32     maxItems: 1
   33 
   34   clocks:
   35     items:
   36       - description: Reference clock.
   37 
   38   clock-names:
   39     items:
   40       - const: ref
   41 
   42   vdd-apc-supply:
   43     description: APC regulator supply.
   44 
   45   '#power-domain-cells':
   46     const: 0
   47 
   48   operating-points-v2:
   49     description: |
   50       A phandle to the OPP table containing the performance states
   51       supported by the CPR power domain.
   52 
   53   acc-syscon:
   54     $ref: /schemas/types.yaml#/definitions/phandle
   55     description: A phandle to the syscon used for writing ACC settings.
   56 
   57   nvmem-cells:
   58     items:
   59       - description: Corner 1 quotient offset
   60       - description: Corner 2 quotient offset
   61       - description: Corner 3 quotient offset
   62       - description: Corner 1 initial voltage
   63       - description: Corner 2 initial voltage
   64       - description: Corner 3 initial voltage
   65       - description: Corner 1 quotient
   66       - description: Corner 2 quotient
   67       - description: Corner 3 quotient
   68       - description: Corner 1 ring oscillator
   69       - description: Corner 2 ring oscillator
   70       - description: Corner 3 ring oscillator
   71       - description: Fuse revision
   72 
   73   nvmem-cell-names:
   74     items:
   75       - const: cpr_quotient_offset1
   76       - const: cpr_quotient_offset2
   77       - const: cpr_quotient_offset3
   78       - const: cpr_init_voltage1
   79       - const: cpr_init_voltage2
   80       - const: cpr_init_voltage3
   81       - const: cpr_quotient1
   82       - const: cpr_quotient2
   83       - const: cpr_quotient3
   84       - const: cpr_ring_osc1
   85       - const: cpr_ring_osc2
   86       - const: cpr_ring_osc3
   87       - const: cpr_fuse_revision
   88 
   89 required:
   90   - compatible
   91   - reg
   92   - interrupts
   93   - clocks
   94   - clock-names
   95   - vdd-apc-supply
   96   - '#power-domain-cells'
   97   - operating-points-v2
   98   - nvmem-cells
   99   - nvmem-cell-names
  100 
  101 additionalProperties: false
  102 
  103 examples:
  104   - |
  105     #include <dt-bindings/interrupt-controller/arm-gic.h>
  106 
  107     cpr_opp_table: opp-table-cpr {
  108         compatible = "operating-points-v2-qcom-level";
  109 
  110         cpr_opp1: opp1 {
  111             opp-level = <1>;
  112             qcom,opp-fuse-level = <1>;
  113         };
  114         cpr_opp2: opp2 {
  115             opp-level = <2>;
  116             qcom,opp-fuse-level = <2>;
  117         };
  118         cpr_opp3: opp3 {
  119             opp-level = <3>;
  120             qcom,opp-fuse-level = <3>;
  121         };
  122     };
  123 
  124     power-controller@b018000 {
  125         compatible = "qcom,qcs404-cpr", "qcom,cpr";
  126         reg = <0x0b018000 0x1000>;
  127         interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
  128         clocks = <&xo_board>;
  129         clock-names = "ref";
  130         vdd-apc-supply = <&pms405_s3>;
  131         #power-domain-cells = <0>;
  132         operating-points-v2 = <&cpr_opp_table>;
  133         acc-syscon = <&tcsr>;
  134 
  135         nvmem-cells = <&cpr_efuse_quot_offset1>,
  136             <&cpr_efuse_quot_offset2>,
  137             <&cpr_efuse_quot_offset3>,
  138             <&cpr_efuse_init_voltage1>,
  139             <&cpr_efuse_init_voltage2>,
  140             <&cpr_efuse_init_voltage3>,
  141             <&cpr_efuse_quot1>,
  142             <&cpr_efuse_quot2>,
  143             <&cpr_efuse_quot3>,
  144             <&cpr_efuse_ring1>,
  145             <&cpr_efuse_ring2>,
  146             <&cpr_efuse_ring3>,
  147             <&cpr_efuse_revision>;
  148         nvmem-cell-names = "cpr_quotient_offset1",
  149             "cpr_quotient_offset2",
  150             "cpr_quotient_offset3",
  151             "cpr_init_voltage1",
  152             "cpr_init_voltage2",
  153             "cpr_init_voltage3",
  154             "cpr_quotient1",
  155             "cpr_quotient2",
  156             "cpr_quotient3",
  157             "cpr_ring_osc1",
  158             "cpr_ring_osc2",
  159             "cpr_ring_osc3",
  160             "cpr_fuse_revision";
  161     };

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sys/contrib/device-tree/Bindings/power/avs/qcom,cpr.yaml