mediatek,power-controller.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Mediatek Power Domains Controller
    8 
    9 maintainers:
   10   - Weiyi Lu <weiyi.lu@mediatek.com>
   11   - Matthias Brugger <mbrugger@suse.com>
   12 
   13 description: |
   14   Mediatek processors include support for multiple power domains which can be
   15   powered up/down by software based on different application scenes to save power.
   16 
   17   IP cores belonging to a power domain should contain a 'power-domains'
   18   property that is a phandle for SCPSYS node representing the domain.
   19 
   20 properties:
   21   $nodename:
   22     const: power-controller
   23 
   24   compatible:
   25     enum:
   26       - mediatek,mt6795-power-controller
   27       - mediatek,mt8167-power-controller
   28       - mediatek,mt8173-power-controller
   29       - mediatek,mt8183-power-controller
   30       - mediatek,mt8186-power-controller
   31       - mediatek,mt8192-power-controller
   32       - mediatek,mt8195-power-controller
   33 
   34   '#power-domain-cells':
   35     const: 1
   36 
   37   '#address-cells':
   38     const: 1
   39 
   40   '#size-cells':
   41     const: 0
   42 
   43 patternProperties:
   44   "^power-domain@[0-9a-f]+$":
   45     type: object
   46     description: |
   47       Represents the power domains within the power controller node as documented
   48       in Documentation/devicetree/bindings/power/power-domain.yaml.
   49 
   50     properties:
   51 
   52       '#power-domain-cells':
   53         description:
   54           Must be 0 for nodes representing a single PM domain and 1 for nodes
   55           providing multiple PM domains.
   56 
   57       '#address-cells':
   58         const: 1
   59 
   60       '#size-cells':
   61         const: 0
   62 
   63       reg:
   64         description: |
   65           Power domain index. Valid values are defined in:
   66               "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain.
   67               "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
   68               "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
   69               "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
   70               "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
   71               "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
   72         maxItems: 1
   73 
   74       clocks:
   75         description: |
   76           A number of phandles to clocks that need to be enabled during domain
   77           power-up sequencing.
   78 
   79       clock-names:
   80         description: |
   81           List of names of clocks, in order to match the power-up sequencing
   82           for each power domain we need to group the clocks by name. BASIC
   83           clocks need to be enabled before enabling the corresponding power
   84           domain, and should not have a '-' in their name (i.e mm, mfg, venc).
   85           SUSBYS clocks need to be enabled before releasing the bus protection,
   86           and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
   87 
   88           In order to follow properly the power-up sequencing, the clocks must
   89           be specified by order, adding first the BASIC clocks followed by the
   90           SUSBSYS clocks.
   91 
   92       domain-supply:
   93         description: domain regulator supply.
   94 
   95       mediatek,infracfg:
   96         $ref: /schemas/types.yaml#/definitions/phandle
   97         description: phandle to the device containing the INFRACFG register range.
   98 
   99       mediatek,smi:
  100         $ref: /schemas/types.yaml#/definitions/phandle
  101         description: phandle to the device containing the SMI register range.
  102 
  103     patternProperties:
  104       "^power-domain@[0-9a-f]+$":
  105         type: object
  106         description: |
  107           Represents a power domain child within a power domain parent node.
  108 
  109         properties:
  110 
  111           '#power-domain-cells':
  112             description:
  113               Must be 0 for nodes representing a single PM domain and 1 for nodes
  114               providing multiple PM domains.
  115 
  116           '#address-cells':
  117             const: 1
  118 
  119           '#size-cells':
  120             const: 0
  121 
  122           reg:
  123             maxItems: 1
  124 
  125           clocks:
  126             description: |
  127               A number of phandles to clocks that need to be enabled during domain
  128               power-up sequencing.
  129 
  130           clock-names:
  131             description: |
  132               List of names of clocks, in order to match the power-up sequencing
  133               for each power domain we need to group the clocks by name. BASIC
  134               clocks need to be enabled before enabling the corresponding power
  135               domain, and should not have a '-' in their name (i.e mm, mfg, venc).
  136               SUSBYS clocks need to be enabled before releasing the bus protection,
  137               and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
  138 
  139               In order to follow properly the power-up sequencing, the clocks must
  140               be specified by order, adding first the BASIC clocks followed by the
  141               SUSBSYS clocks.
  142 
  143           domain-supply:
  144             description: domain regulator supply.
  145 
  146           mediatek,infracfg:
  147             $ref: /schemas/types.yaml#/definitions/phandle
  148             description: phandle to the device containing the INFRACFG register range.
  149 
  150           mediatek,smi:
  151             $ref: /schemas/types.yaml#/definitions/phandle
  152             description: phandle to the device containing the SMI register range.
  153 
  154         patternProperties:
  155           "^power-domain@[0-9a-f]+$":
  156             type: object
  157             description: |
  158               Represents a power domain child within a power domain parent node.
  159 
  160             properties:
  161 
  162               '#power-domain-cells':
  163                 description:
  164                   Must be 0 for nodes representing a single PM domain and 1 for nodes
  165                   providing multiple PM domains.
  166 
  167               '#address-cells':
  168                 const: 1
  169 
  170               '#size-cells':
  171                 const: 0
  172 
  173               reg:
  174                 maxItems: 1
  175 
  176               clocks:
  177                 description: |
  178                   A number of phandles to clocks that need to be enabled during domain
  179                   power-up sequencing.
  180 
  181               clock-names:
  182                 description: |
  183                   List of names of clocks, in order to match the power-up sequencing
  184                   for each power domain we need to group the clocks by name. BASIC
  185                   clocks need to be enabled before enabling the corresponding power
  186                   domain, and should not have a '-' in their name (i.e mm, mfg, venc).
  187                   SUSBYS clocks need to be enabled before releasing the bus protection,
  188                   and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
  189 
  190                   In order to follow properly the power-up sequencing, the clocks must
  191                   be specified by order, adding first the BASIC clocks followed by the
  192                   SUSBSYS clocks.
  193 
  194               domain-supply:
  195                 description: domain regulator supply.
  196 
  197               mediatek,infracfg:
  198                 $ref: /schemas/types.yaml#/definitions/phandle
  199                 description: phandle to the device containing the INFRACFG register range.
  200 
  201               mediatek,smi:
  202                 $ref: /schemas/types.yaml#/definitions/phandle
  203                 description: phandle to the device containing the SMI register range.
  204 
  205             required:
  206               - reg
  207 
  208             additionalProperties: false
  209 
  210         required:
  211           - reg
  212 
  213         additionalProperties: false
  214 
  215     required:
  216       - reg
  217 
  218     additionalProperties: false
  219 
  220 required:
  221   - compatible
  222 
  223 additionalProperties: false
  224 
  225 examples:
  226   - |
  227     #include <dt-bindings/clock/mt8173-clk.h>
  228     #include <dt-bindings/power/mt8173-power.h>
  229 
  230     soc {
  231         #address-cells = <2>;
  232         #size-cells = <2>;
  233 
  234         scpsys: syscon@10006000 {
  235             compatible = "syscon", "simple-mfd";
  236             reg = <0 0x10006000 0 0x1000>;
  237 
  238             spm: power-controller {
  239                 compatible = "mediatek,mt8173-power-controller";
  240                 #address-cells = <1>;
  241                 #size-cells = <0>;
  242                 #power-domain-cells = <1>;
  243 
  244                 /* power domains of the SoC */
  245                 power-domain@MT8173_POWER_DOMAIN_VDEC {
  246                     reg = <MT8173_POWER_DOMAIN_VDEC>;
  247                     clocks = <&topckgen CLK_TOP_MM_SEL>;
  248                     clock-names = "mm";
  249                     #power-domain-cells = <0>;
  250                 };
  251                 power-domain@MT8173_POWER_DOMAIN_VENC {
  252                     reg = <MT8173_POWER_DOMAIN_VENC>;
  253                     clocks = <&topckgen CLK_TOP_MM_SEL>,
  254                              <&topckgen CLK_TOP_VENC_SEL>;
  255                     clock-names = "mm", "venc";
  256                     #power-domain-cells = <0>;
  257                 };
  258                 power-domain@MT8173_POWER_DOMAIN_ISP {
  259                     reg = <MT8173_POWER_DOMAIN_ISP>;
  260                     clocks = <&topckgen CLK_TOP_MM_SEL>;
  261                     clock-names = "mm";
  262                     #power-domain-cells = <0>;
  263                 };
  264                 power-domain@MT8173_POWER_DOMAIN_MM {
  265                     reg = <MT8173_POWER_DOMAIN_MM>;
  266                     clocks = <&topckgen CLK_TOP_MM_SEL>;
  267                     clock-names = "mm";
  268                     #power-domain-cells = <0>;
  269                     mediatek,infracfg = <&infracfg>;
  270                 };
  271                 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
  272                     reg = <MT8173_POWER_DOMAIN_VENC_LT>;
  273                     clocks = <&topckgen CLK_TOP_MM_SEL>,
  274                              <&topckgen CLK_TOP_VENC_LT_SEL>;
  275                     clock-names = "mm", "venclt";
  276                     #power-domain-cells = <0>;
  277                 };
  278                 power-domain@MT8173_POWER_DOMAIN_AUDIO {
  279                     reg = <MT8173_POWER_DOMAIN_AUDIO>;
  280                     #power-domain-cells = <0>;
  281                 };
  282                 power-domain@MT8173_POWER_DOMAIN_USB {
  283                     reg = <MT8173_POWER_DOMAIN_USB>;
  284                     #power-domain-cells = <0>;
  285                 };
  286                 power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
  287                     reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
  288                     clocks = <&clk26m>;
  289                     clock-names = "mfg";
  290                     #address-cells = <1>;
  291                     #size-cells = <0>;
  292                     #power-domain-cells = <1>;
  293 
  294                     power-domain@MT8173_POWER_DOMAIN_MFG_2D {
  295                         reg = <MT8173_POWER_DOMAIN_MFG_2D>;
  296                         #address-cells = <1>;
  297                         #size-cells = <0>;
  298                         #power-domain-cells = <1>;
  299 
  300                         power-domain@MT8173_POWER_DOMAIN_MFG {
  301                             reg = <MT8173_POWER_DOMAIN_MFG>;
  302                             #power-domain-cells = <0>;
  303                             mediatek,infracfg = <&infracfg>;
  304                         };
  305                     };
  306                 };
  307             };
  308         };
  309     };
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