mpic.txt

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    1 =====================================================================
    2 Freescale MPIC Interrupt Controller Node
    3 Copyright (C) 2010,2011 Freescale Semiconductor Inc.
    4 =====================================================================
    5 
    6 The Freescale MPIC interrupt controller is found on all PowerQUICC
    7 and QorIQ processors and is compatible with the Open PIC.  The
    8 notable difference from Open PIC binding is the addition of 2
    9 additional cells in the interrupt specifier defining interrupt type
   10 information.
   11 
   12 PROPERTIES
   13 
   14   - compatible
   15       Usage: required
   16       Value type: <string>
   17       Definition: Shall include "fsl,mpic".  Freescale MPIC
   18           controllers compatible with this binding have Block
   19           Revision Registers BRR1 and BRR2 at offset 0x0 and
   20           0x10 in the MPIC.
   21 
   22   - reg
   23       Usage: required
   24       Value type: <prop-encoded-array>
   25       Definition: A standard property.  Specifies the physical
   26           offset and length of the device's registers within the
   27           CCSR address space.
   28 
   29   - interrupt-controller
   30       Usage: required
   31       Value type: <empty>
   32       Definition: Specifies that this node is an interrupt
   33           controller
   34 
   35   - #interrupt-cells
   36       Usage: required
   37       Value type: <u32>
   38       Definition: Shall be 2 or 4.  A value of 2 means that interrupt
   39           specifiers do not contain the interrupt-type or type-specific
   40           information cells.
   41 
   42   - #address-cells
   43       Usage: required
   44       Value type: <u32>
   45       Definition: Shall be 0.
   46 
   47   - pic-no-reset
   48       Usage: optional
   49       Value type: <empty>
   50       Definition: The presence of this property specifies that the
   51           MPIC must not be reset by the client program, and that
   52           the boot program has initialized all interrupt source
   53           configuration registers to a sane state-- masked or
   54           directed at other cores.  This ensures that the client
   55           program will not receive interrupts for sources not belonging
   56           to the client.  The presence of this property also mandates
   57           that any initialization related to interrupt sources shall
   58           be limited to sources explicitly referenced in the device tree.
   59 
   60   - big-endian
   61       Usage: optional
   62       Value type: <empty>
   63           If present the MPIC will be assumed to be big-endian.  Some
   64           device-trees omit this property on MPIC nodes even when the MPIC is
   65           in fact big-endian, so certain boards override this property.
   66 
   67   - single-cpu-affinity
   68       Usage: optional
   69       Value type: <empty>
   70           If present the MPIC will be assumed to only be able to route
   71           non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).
   72 
   73   - last-interrupt-source
   74       Usage: optional
   75       Value type: <u32>
   76           Some MPICs do not correctly report the number of hardware sources
   77           in the global feature registers.  If specified, this field will
   78           override the value read from MPIC_GREG_FEATURE_LAST_SRC.
   79 
   80 INTERRUPT SPECIFIER DEFINITION
   81 
   82   Interrupt specifiers consists of 4 cells encoded as
   83   follows:
   84 
   85    <1st-cell>   interrupt-number
   86 
   87                 Identifies the interrupt source.  The meaning
   88                 depends on the type of interrupt.
   89 
   90                 Note: If the interrupt-type cell is undefined
   91                 (i.e. #interrupt-cells = 2), this cell
   92                 should be interpreted the same as for
   93                 interrupt-type 0-- i.e. an external or
   94                 normal SoC device interrupt.
   95 
   96    <2nd-cell>   level-sense information, encoded as follows:
   97                     0 = low-to-high edge triggered
   98                     1 = active low level-sensitive
   99                     2 = active high level-sensitive
  100                     3 = high-to-low edge triggered
  101 
  102    <3rd-cell>   interrupt-type
  103 
  104                 The following types are supported:
  105 
  106                   0 = external or normal SoC device interrupt
  107 
  108                       The interrupt-number cell contains
  109                       the SoC device interrupt number.  The
  110                       type-specific cell is undefined.  The
  111                       interrupt-number is derived from the
  112                       MPIC a block of registers referred to as
  113                       the "Interrupt Source Configuration Registers".
  114                       Each source has 32-bytes of registers
  115                       (vector/priority and destination) in this
  116                       region.   So interrupt 0 is at offset 0x0,
  117                       interrupt 1 is at offset 0x20, and so on.
  118 
  119                   1 = error interrupt
  120 
  121                       The interrupt-number cell contains
  122                       the SoC device interrupt number for
  123                       the error interrupt.  The type-specific
  124                       cell identifies the specific error
  125                       interrupt number.
  126 
  127                   2 = MPIC inter-processor interrupt (IPI)
  128 
  129                       The interrupt-number cell identifies
  130                       the MPIC IPI number.  The type-specific
  131                       cell is undefined.
  132 
  133                   3 = MPIC timer interrupt
  134 
  135                       The interrupt-number cell identifies
  136                       the MPIC timer number.  The type-specific
  137                       cell is undefined.
  138 
  139    <4th-cell>   type-specific information
  140 
  141                 The type-specific cell is encoded as follows:
  142 
  143                  - For interrupt-type 1 (error interrupt),
  144                    the type-specific cell contains the
  145                    bit number of the error interrupt in the
  146                    Error Interrupt Summary Register.
  147 
  148 EXAMPLE 1
  149         /*
  150          * mpic interrupt controller with 4 cells per specifier
  151          */
  152         mpic: pic@40000 {
  153                 compatible = "fsl,mpic";
  154                 interrupt-controller;
  155                 #interrupt-cells = <4>;
  156                 #address-cells = <0>;
  157                 reg = <0x40000 0x40000>;
  158         };
  159 
  160 EXAMPLE 2
  161         /*
  162          * The MPC8544 I2C controller node has an internal
  163          * interrupt number of 27.  As per the reference manual
  164          * this corresponds to interrupt source configuration
  165          * registers at 0x5_0560.
  166          *
  167          * The interrupt source configuration registers begin
  168          * at 0x5_0000.
  169          *
  170          * To compute the interrupt specifier interrupt number
  171          *
  172          *       0x560 >> 5 = 43
  173          *
  174          * The interrupt source configuration registers begin
  175          * at 0x5_0000, and so the i2c vector/priority registers
  176          * are at 0x5_0560.
  177          */
  178         i2c@3000 {
  179                 #address-cells = <1>;
  180                 #size-cells = <0>;
  181                 cell-index = <0>;
  182                 compatible = "fsl-i2c";
  183                 reg = <0x3000 0x100>;
  184                 interrupts = <43 2>;
  185                 interrupt-parent = <&mpic>;
  186                 dfsrr;
  187         };
  188 
  189 
  190 EXAMPLE 3
  191         /*
  192          *  Definition of a node defining the 4
  193          *  MPIC IPI interrupts.  Note the interrupt
  194          *  type of 2.
  195          */
  196         ipi@410a0 {
  197                 compatible = "fsl,mpic-ipi";
  198                 reg = <0x40040 0x10>;
  199                 interrupts = <0 0 2 0
  200                               1 0 2 0
  201                               2 0 2 0
  202                               3 0 2 0>;
  203         };
  204 
  205 EXAMPLE 4
  206         /*
  207          *  Definition of a node defining the MPIC
  208          *  global timers.  Note the interrupt
  209          *  type of 3.
  210          */
  211         timer0: timer@41100 {
  212                 compatible = "fsl,mpic-global-timer";
  213                 reg = <0x41100 0x100 0x41300 4>;
  214                 interrupts = <0 0 3 0
  215                               1 0 3 0
  216                               2 0 3 0
  217                               3 0 3 0>;
  218         };
  219 
  220 EXAMPLE 5
  221         /*
  222          * Definition of an error interrupt (interrupt type 1).
  223          * SoC interrupt number is 16 and the specific error
  224          * interrupt bit in the error interrupt summary register
  225          * is 23.
  226          */
  227         memory-controller@8000 {
  228                 compatible = "fsl,p4080-memory-controller";
  229                 reg = <0x8000 0x1000>;
  230                 interrupts = <16 2 1 23>;
  231         };

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