microchip,corepwm.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 
    3 %YAML 1.2
    4 ---
    5 $id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
    6 $schema: http://devicetree.org/meta-schemas/core.yaml#
    7 
    8 title: Microchip IP corePWM controller bindings
    9 
   10 maintainers:
   11   - Conor Dooley <conor.dooley@microchip.com>
   12 
   13 description: |
   14   corePWM is an 16 channel pulse width modulator FPGA IP
   15 
   16   https://www.microsemi.com/existing-parts/parts/152118
   17 
   18 allOf:
   19   - $ref: pwm.yaml#
   20 
   21 properties:
   22   compatible:
   23     items:
   24       - const: microchip,corepwm-rtl-v4
   25 
   26   reg:
   27     maxItems: 1
   28 
   29   clocks:
   30     maxItems: 1
   31 
   32   "#pwm-cells":
   33     const: 2
   34 
   35   microchip,sync-update-mask:
   36     description: |
   37       Depending on how the IP is instantiated, there are two modes of operation.
   38       In synchronous mode, all channels are updated at the beginning of the PWM period,
   39       and in asynchronous mode updates happen as the control registers are written.
   40       A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
   41       mode is possible for each channel, and is set by the bitstream programmed to the
   42       FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that
   43       control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.
   44       At runtime a bit wide register exposed to APB can be used to toggle on/off
   45       synchronised mode for all channels it has been synthesised for.
   46       Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
   47       whether synchronous mode is possible for the PWM channel.
   48 
   49     $ref: /schemas/types.yaml#/definitions/uint32
   50     default: 0
   51 
   52   microchip,dac-mode-mask:
   53     description: |
   54       Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
   55       a minimum period pulse train whose High/Low average is that of the chosen duty
   56       cycle. This "DAC" will have far better bandwidth and ripple performance than the
   57       standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
   58       core, set at instantiation and by the bitstream programmed to the FPGA, determines
   59       whether a given channel operates in regular PWM or DAC mode.
   60       Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
   61       for that channel.
   62 
   63     $ref: /schemas/types.yaml#/definitions/uint32
   64     default: 0
   65 
   66 required:
   67   - compatible
   68   - reg
   69   - clocks
   70 
   71 additionalProperties: false
   72 
   73 examples:
   74   - |
   75     pwm@41000000 {
   76       compatible = "microchip,corepwm-rtl-v4";
   77       microchip,sync-update-mask = /bits/ 32 <0>;
   78       clocks = <&clkcfg 30>;
   79       reg = <0x41000000 0xF0>;
   80       #pwm-cells = <2>;
   81     };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/pwm/microchip,corepwm.yaml

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/pwm/microchip,corepwm.yaml