1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Renesas R-Car PWM Timer Controller
8
9 maintainers:
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
11
12 properties:
13 compatible:
14 items:
15 - enum:
16 - renesas,pwm-r8a7742 # RZ/G1H
17 - renesas,pwm-r8a7743 # RZ/G1M
18 - renesas,pwm-r8a7744 # RZ/G1N
19 - renesas,pwm-r8a7745 # RZ/G1E
20 - renesas,pwm-r8a77470 # RZ/G1C
21 - renesas,pwm-r8a774a1 # RZ/G2M
22 - renesas,pwm-r8a774b1 # RZ/G2N
23 - renesas,pwm-r8a774c0 # RZ/G2E
24 - renesas,pwm-r8a774e1 # RZ/G2H
25 - renesas,pwm-r8a7778 # R-Car M1A
26 - renesas,pwm-r8a7779 # R-Car H1
27 - renesas,pwm-r8a7790 # R-Car H2
28 - renesas,pwm-r8a7791 # R-Car M2-W
29 - renesas,pwm-r8a7794 # R-Car E2
30 - renesas,pwm-r8a7795 # R-Car H3
31 - renesas,pwm-r8a7796 # R-Car M3-W
32 - renesas,pwm-r8a77961 # R-Car M3-W+
33 - renesas,pwm-r8a77965 # R-Car M3-N
34 - renesas,pwm-r8a77970 # R-Car V3M
35 - renesas,pwm-r8a77980 # R-Car V3H
36 - renesas,pwm-r8a77990 # R-Car E3
37 - renesas,pwm-r8a77995 # R-Car D3
38 - const: renesas,pwm-rcar
39
40 reg:
41 # base address and length of the registers block for the PWM.
42 maxItems: 1
43
44 '#pwm-cells':
45 # should be 2. See pwm.yaml in this directory for a description of
46 # the cells format.
47 const: 2
48
49 clocks:
50 # clock phandle and specifier pair.
51 maxItems: 1
52
53 power-domains:
54 maxItems: 1
55
56 resets:
57 maxItems: 1
58
59 required:
60 - compatible
61 - reg
62 - clocks
63 - power-domains
64
65 allOf:
66 - $ref: pwm.yaml#
67
68 - if:
69 not:
70 properties:
71 compatible:
72 contains:
73 enum:
74 - renesas,pwm-r8a7778
75 - renesas,pwm-r8a7779
76 then:
77 required:
78 - resets
79
80 additionalProperties: false
81
82 examples:
83 - |
84 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
85 #include <dt-bindings/power/r8a7743-sysc.h>
86
87 pwm0: pwm@e6e30000 {
88 compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
89 reg = <0xe6e30000 0x8>;
90 clocks = <&cpg CPG_MOD 523>;
91 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
92 resets = <&cpg 523>;
93 #pwm-cells = <2>;
94 pinctrl-0 = <&pwm0_pins>;
95 pinctrl-names = "default";
96 };
Cache object: f0284cd10d7ea32f000bf028d8efb7b6
|