sifive-l2-cache.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
    2 # Copyright (C) 2020 SiFive, Inc.
    3 %YAML 1.2
    4 ---
    5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
    6 $schema: http://devicetree.org/meta-schemas/core.yaml#
    7 
    8 title: SiFive L2 Cache Controller
    9 
   10 maintainers:
   11   - Sagar Kadam <sagar.kadam@sifive.com>
   12   - Paul Walmsley  <paul.walmsley@sifive.com>
   13 
   14 description:
   15   The SiFive Level 2 Cache Controller is used to provide access to fast copies
   16   of memory for masters in a Core Complex. The Level 2 Cache Controller also
   17   acts as directory-based coherency manager.
   18   All the properties in ePAPR/DeviceTree specification applies for this platform.
   19 
   20 select:
   21   properties:
   22     compatible:
   23       contains:
   24         enum:
   25           - sifive,fu540-c000-ccache
   26           - sifive,fu740-c000-ccache
   27 
   28   required:
   29     - compatible
   30 
   31 properties:
   32   compatible:
   33     oneOf:
   34       - items:
   35           - enum:
   36               - sifive,fu540-c000-ccache
   37               - sifive,fu740-c000-ccache
   38           - const: cache
   39       - items:
   40           - const: microchip,mpfs-ccache
   41           - const: sifive,fu540-c000-ccache
   42           - const: cache
   43 
   44   cache-block-size:
   45     const: 64
   46 
   47   cache-level:
   48     const: 2
   49 
   50   cache-sets:
   51     enum: [1024, 2048]
   52 
   53   cache-size:
   54     const: 2097152
   55 
   56   cache-unified: true
   57 
   58   interrupts:
   59     minItems: 3
   60     items:
   61       - description: DirError interrupt
   62       - description: DataError interrupt
   63       - description: DataFail interrupt
   64       - description: DirFail interrupt
   65 
   66   reg:
   67     maxItems: 1
   68 
   69   next-level-cache: true
   70 
   71   memory-region:
   72     maxItems: 1
   73     description: |
   74       The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
   75       The reserved memory node should be defined as per the bindings in reserved-memory.txt.
   76 
   77 allOf:
   78   - $ref: /schemas/cache-controller.yaml#
   79 
   80   - if:
   81       properties:
   82         compatible:
   83           contains:
   84             enum:
   85               - sifive,fu740-c000-ccache
   86               - microchip,mpfs-ccache
   87 
   88     then:
   89       properties:
   90         interrupts:
   91           description: |
   92             Must contain entries for DirError, DataError, DataFail, DirFail signals.
   93           minItems: 4
   94 
   95     else:
   96       properties:
   97         interrupts:
   98           description: |
   99             Must contain entries for DirError, DataError and DataFail signals.
  100           maxItems: 3
  101 
  102   - if:
  103       properties:
  104         compatible:
  105           contains:
  106             const: sifive,fu740-c000-ccache
  107 
  108     then:
  109       properties:
  110         cache-sets:
  111           const: 2048
  112 
  113     else:
  114       properties:
  115         cache-sets:
  116           const: 1024
  117 
  118 additionalProperties: false
  119 
  120 required:
  121   - compatible
  122   - cache-block-size
  123   - cache-level
  124   - cache-sets
  125   - cache-size
  126   - cache-unified
  127   - interrupts
  128   - reg
  129 
  130 examples:
  131   - |
  132     cache-controller@2010000 {
  133         compatible = "sifive,fu540-c000-ccache", "cache";
  134         cache-block-size = <64>;
  135         cache-level = <2>;
  136         cache-sets = <1024>;
  137         cache-size = <2097152>;
  138         cache-unified;
  139         reg = <0x2010000 0x1000>;
  140         interrupt-parent = <&plic0>;
  141         interrupts = <1>,
  142                      <2>,
  143                      <3>;
  144         next-level-cache = <&L25>;
  145         memory-region = <&l2_lim>;
  146     };

Cache object: 0e2b94cd795993f6009b273f515d3949

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/riscv/sifive-l2-cache.yaml

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/riscv/sifive-l2-cache.yaml