mediatek,uart.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
    8 
    9 maintainers:
   10   - Matthias Brugger <matthias.bgg@gmail.com>
   11 
   12 allOf:
   13   - $ref: serial.yaml#
   14 
   15 description: |
   16   The MediaTek UART is based on the basic 8250 UART and compatible
   17   with 16550A, with enhancements for high speed baud rates and
   18   support for DMA.
   19 
   20 properties:
   21   compatible:
   22     oneOf:
   23       - const: mediatek,mt6577-uart
   24       - items:
   25           - enum:
   26               - mediatek,mt2701-uart
   27               - mediatek,mt2712-uart
   28               - mediatek,mt6580-uart
   29               - mediatek,mt6582-uart
   30               - mediatek,mt6589-uart
   31               - mediatek,mt6755-uart
   32               - mediatek,mt6765-uart
   33               - mediatek,mt6779-uart
   34               - mediatek,mt6795-uart
   35               - mediatek,mt6797-uart
   36               - mediatek,mt7622-uart
   37               - mediatek,mt7623-uart
   38               - mediatek,mt7629-uart
   39               - mediatek,mt7986-uart
   40               - mediatek,mt8127-uart
   41               - mediatek,mt8135-uart
   42               - mediatek,mt8173-uart
   43               - mediatek,mt8183-uart
   44               - mediatek,mt8186-uart
   45               - mediatek,mt8192-uart
   46               - mediatek,mt8195-uart
   47               - mediatek,mt8516-uart
   48           - const: mediatek,mt6577-uart
   49 
   50   reg:
   51     description: The base address of the UART register bank
   52     maxItems: 1
   53 
   54   clocks:
   55     minItems: 1
   56     items:
   57       - description: The clock the baudrate is derived from
   58       - description: The bus clock for register accesses
   59 
   60   clock-names:
   61     minItems: 1
   62     items:
   63       - const: baud
   64       - const: bus
   65 
   66   dmas:
   67     items:
   68       - description: phandle to TX DMA
   69       - description: phandle to RX DMA
   70 
   71   dma-names:
   72     items:
   73       - const: tx
   74       - const: rx
   75 
   76   interrupts:
   77     minItems: 1
   78     maxItems: 2
   79 
   80   interrupt-names:
   81     description:
   82       The UART interrupt and optionally the RX in-band wakeup interrupt.
   83     minItems: 1
   84     items:
   85       - const: uart
   86       - const: wakeup
   87 
   88   pinctrl-0: true
   89   pinctrl-1: true
   90 
   91   pinctrl-names:
   92     minItems: 1
   93     items:
   94       - const: default
   95       - const: sleep
   96 
   97 required:
   98   - compatible
   99   - reg
  100   - clocks
  101   - interrupts
  102 
  103 unevaluatedProperties: false
  104 
  105 examples:
  106   - |
  107     #include <dt-bindings/interrupt-controller/arm-gic.h>
  108 
  109     serial@11006000 {
  110         compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart";
  111         reg = <0x11006000 0x400>;
  112         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
  113                      <GIC_SPI 52 IRQ_TYPE_EDGE_FALLING>;
  114         interrupt-names = "uart", "wakeup";
  115         clocks = <&uart_clk>, <&bus_clk>;
  116         clock-names = "baud", "bus";
  117         pinctrl-0 = <&uart_pin>;
  118         pinctrl-1 = <&uart_pin_sleep>;
  119         pinctrl-names = "default", "sleep";
  120     };

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sys/contrib/device-tree/Bindings/serial/mediatek,uart.yaml