| 
     1 * CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter *
    2 
    3 Required properties:
    4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
    5                 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
    6 - reg : Offset and length of the register set for the device
    7 - interrupts : Should contain uart interrupt
    8 - fifosize : Should define hardware rx/tx fifo size
    9 - clocks : Should contain uart clock number
   10 
   11 Optional properties:
   12 - uart-has-rtscts: we have hardware flow controller pins in hardware
   13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
   14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
   15 
   16 Example:
   17 
   18 uart0: uart@b0050000 {
   19         cell-index = <0>;
   20         compatible = "sirf,prima2-uart";
   21         reg = <0xb0050000 0x1000>;
   22         interrupts = <17>;
   23         fifosize = <128>;
   24         clocks = <&clks 13>;
   25 };
   26 
   27 On the board-specific dts, we can put rts-gpios and cts-gpios like
   28 
   29 usp@b0090000 {
   30         compatible = "sirf,prima2-usp-uart";
   31         uart-has-rtscts;
   32         rts-gpios = <&gpio 15 0>;
   33         cts-gpios = <&gpio 46 0>;
   34 };
Cache object: 3916b85b195fbed92790377bb137b701 
 
 |