The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: NXP i.MX8MP Media Block Control
    8 
    9 maintainers:
   10   - Paul Elder <paul.elder@ideasonboard.com>
   11 
   12 description:
   13   The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
   14   providing access to the NoC and ensuring proper power sequencing of the
   15   peripherals within the MEDIAMIX domain.
   16 
   17 properties:
   18   compatible:
   19     items:
   20       - const: fsl,imx8mp-media-blk-ctrl
   21       - const: syscon
   22 
   23   reg:
   24     maxItems: 1
   25 
   26   '#power-domain-cells':
   27     const: 1
   28 
   29   power-domains:
   30     maxItems: 10
   31 
   32   power-domain-names:
   33     items:
   34       - const: bus
   35       - const: mipi-dsi1
   36       - const: mipi-csi1
   37       - const: lcdif1
   38       - const: isi
   39       - const: mipi-csi2
   40       - const: lcdif2
   41       - const: isp
   42       - const: dwe
   43       - const: mipi-dsi2
   44 
   45   clocks:
   46     items:
   47       - description: The APB clock
   48       - description: The AXI clock
   49       - description: The pixel clock for the first CSI2 receiver (aclk)
   50       - description: The pixel clock for the second CSI2 receiver (aclk)
   51       - description: The pixel clock for the first LCDIF (pix_clk)
   52       - description: The pixel clock for the second LCDIF (pix_clk)
   53       - description: The core clock for the ISP (clk)
   54       - description: The MIPI-PHY reference clock used by DSI
   55 
   56   clock-names:
   57     items:
   58       - const: apb
   59       - const: axi
   60       - const: cam1
   61       - const: cam2
   62       - const: disp1
   63       - const: disp2
   64       - const: isp
   65       - const: phy
   66 
   67 required:
   68   - compatible
   69   - reg
   70   - '#power-domain-cells'
   71   - power-domains
   72   - power-domain-names
   73   - clocks
   74   - clock-names
   75 
   76 additionalProperties: false
   77 
   78 examples:
   79   - |
   80     #include <dt-bindings/clock/imx8mp-clock.h>
   81     #include <dt-bindings/power/imx8mp-power.h>
   82 
   83     media_blk_ctl: blk-ctl@32ec0000 {
   84         compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
   85         reg = <0x32ec0000 0x138>;
   86         power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
   87                         <&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
   88                         <&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
   89                         <&mipi_phy2_pd>;
   90         power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
   91                              "mipi-csi2", "lcdif2", "isp", "dwe", "mipi-dsi2";
   92         clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
   93                  <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
   94                  <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
   95                  <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
   96                  <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
   97                  <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
   98                  <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
   99                  <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
  100         clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
  101                       "isp", "phy";
  102         #power-domain-cells = <1>;
  103     };
  104 ...

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