| 
     1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: NXP i.MX8MQ VPU blk-ctrl
    8 
    9 maintainers:
   10   - Lucas Stach <l.stach@pengutronix.de>
   11 
   12 description:
   13   The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to
   14   the NoC and ensuring proper power sequencing of the VPU peripherals
   15   located in the VPU domain of the SoC.
   16 
   17 properties:
   18   compatible:
   19     items:
   20       - const: fsl,imx8mq-vpu-blk-ctrl
   21 
   22   reg:
   23     maxItems: 1
   24 
   25   '#power-domain-cells':
   26     const: 1
   27 
   28   power-domains:
   29     minItems: 3
   30     maxItems: 3
   31 
   32   power-domain-names:
   33     items:
   34       - const: bus
   35       - const: g1
   36       - const: g2
   37 
   38   clocks:
   39     minItems: 2
   40     maxItems: 2
   41 
   42   clock-names:
   43     items:
   44       - const: g1
   45       - const: g2
   46 
   47 required:
   48   - compatible
   49   - reg
   50   - power-domains
   51   - power-domain-names
   52   - clocks
   53   - clock-names
   54 
   55 additionalProperties: false
   56 
   57 examples:
   58   - |
   59     #include <dt-bindings/clock/imx8mq-clock.h>
   60     #include <dt-bindings/power/imx8mq-power.h>
   61 
   62     vpu_blk_ctrl: blk-ctrl@38320000 {
   63       compatible = "fsl,imx8mq-vpu-blk-ctrl";
   64       reg = <0x38320000 0x100>;
   65       power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
   66       power-domain-names = "bus", "g1", "g2";
   67       clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
   68                <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
   69       clock-names = "g1", "g2";
   70       #power-domain-cells = <1>;
   71     };
Cache object: f9c7f5570dca5497420c7521389098a7 
 
 |