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     1 Qualcomm Always-On Subsystem side channel binding
    2 
    3 This binding describes the hardware component responsible for side channel
    4 requests to the always-on subsystem (AOSS), used for certain power management
    5 requests that is not handled by the standard RPMh interface. Each client in the
    6 SoC has it's own block of message RAM and IRQ for communication with the AOSS.
    7 The protocol used to communicate in the message RAM is known as Qualcomm
    8 Messaging Protocol (QMP)
    9 
   10 The AOSS side channel exposes control over a set of resources, used to control
   11 a set of debug related clocks and to affect the low power state of resources
   12 related to the secondary subsystems. These resources are exposed as a set of
   13 power-domains.
   14 
   15 - compatible:
   16         Usage: required
   17         Value type: <string>
   18         Definition: must be one of:
   19                     "qcom,sc7180-aoss-qmp"
   20                     "qcom,sc7280-aoss-qmp"
   21                     "qcom,sdm845-aoss-qmp"
   22                     "qcom,sm8150-aoss-qmp"
   23                     "qcom,sm8250-aoss-qmp"
   24                     "qcom,sm8350-aoss-qmp"
   25 
   26 - reg:
   27         Usage: required
   28         Value type: <prop-encoded-array>
   29         Definition: the base address and size of the message RAM for this
   30                     client's communication with the AOSS
   31 
   32 - interrupts:
   33         Usage: required
   34         Value type: <prop-encoded-array>
   35         Definition: should specify the AOSS message IRQ for this client
   36 
   37 - mboxes:
   38         Usage: required
   39         Value type: <prop-encoded-array>
   40         Definition: reference to the mailbox representing the outgoing doorbell
   41                     in APCS for this client, as described in mailbox/mailbox.txt
   42 
   43 - #clock-cells:
   44         Usage: optional
   45         Value type: <u32>
   46         Definition: must be 0
   47                     The single clock represents the QDSS clock.
   48 
   49 - #power-domain-cells:
   50         Usage: optional
   51         Value type: <u32>
   52         Definition: must be 1
   53                     The provided power-domains are:
   54                     CDSP state (0), LPASS state (1), modem state (2), SLPI
   55                     state (3), SPSS state (4) and Venus state (5).
   56 
   57 = SUBNODES
   58 The AOSS side channel also provides the controls for three cooling devices,
   59 these are expressed as subnodes of the QMP node. The name of the node is used
   60 to identify the resource and must therefor be "cx", "mx" or "ebi".
   61 
   62 - #cooling-cells:
   63         Usage: optional
   64         Value type: <u32>
   65         Definition: must be 2
   66 
   67 = EXAMPLE
   68 
   69 The following example represents the AOSS side-channel message RAM and the
   70 mechanism exposing the power-domains, as found in SDM845.
   71 
   72   aoss_qmp: qmp@c300000 {
   73           compatible = "qcom,sdm845-aoss-qmp";
   74           reg = <0x0c300000 0x100000>;
   75           interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
   76           mboxes = <&apss_shared 0>;
   77 
   78           #power-domain-cells = <1>;
   79 
   80           cx_cdev: cx {
   81                 #cooling-cells = <2>;
   82           };
   83 
   84           mx_cdev: mx {
   85                 #cooling-cells = <2>;
   86           };
   87   };
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