qcom,aoss-qmp.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/soc/qcom/qcom,aoss-qmp.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Qualcomm Always-On Subsystem side channel binding
    8 
    9 maintainers:
   10   - Bjorn Andersson <bjorn.andersson@linaro.org>
   11 
   12 description:
   13   This binding describes the hardware component responsible for side channel
   14   requests to the always-on subsystem (AOSS), used for certain power management
   15   requests that is not handled by the standard RPMh interface. Each client in the
   16   SoC has its own block of message RAM and IRQ for communication with the AOSS.
   17   The protocol used to communicate in the message RAM is known as Qualcomm
   18   Messaging Protocol (QMP)
   19 
   20   The AOSS side channel exposes control over a set of resources, used to control
   21   a set of debug related clocks and to affect the low power state of resources
   22   related to the secondary subsystems.
   23 
   24 properties:
   25   compatible:
   26     items:
   27       - enum:
   28           - qcom,sc7180-aoss-qmp
   29           - qcom,sc7280-aoss-qmp
   30           - qcom,sc8180x-aoss-qmp
   31           - qcom,sdm845-aoss-qmp
   32           - qcom,sm6350-aoss-qmp
   33           - qcom,sm8150-aoss-qmp
   34           - qcom,sm8250-aoss-qmp
   35           - qcom,sm8350-aoss-qmp
   36           - qcom,sm8450-aoss-qmp
   37       - const: qcom,aoss-qmp
   38 
   39   reg:
   40     maxItems: 1
   41     description:
   42       The base address and size of the message RAM for this client's
   43       communication with the AOSS
   44 
   45   interrupts:
   46     maxItems: 1
   47     description:
   48       Should specify the AOSS message IRQ for this client
   49 
   50   mboxes:
   51     maxItems: 1
   52     description:
   53       Reference to the mailbox representing the outgoing doorbell in APCS for
   54       this client, as described in mailbox/mailbox.txt
   55 
   56   "#clock-cells":
   57     const: 0
   58     description:
   59       The single clock represents the QDSS clock.
   60 
   61 required:
   62   - compatible
   63   - reg
   64   - interrupts
   65   - mboxes
   66   - "#clock-cells"
   67 
   68 additionalProperties: false
   69 
   70 patternProperties:
   71   "^(cx|mx|ebi)$":
   72     type: object
   73     description:
   74       The AOSS side channel also provides the controls for three cooling devices,
   75       these are expressed as subnodes of the QMP node. The name of the node is
   76       used to identify the resource and must therefor be "cx", "mx" or "ebi".
   77 
   78     properties:
   79       "#cooling-cells":
   80         const: 2
   81 
   82     required:
   83       - "#cooling-cells"
   84 
   85     additionalProperties: false
   86 
   87 examples:
   88   - |
   89     #include <dt-bindings/interrupt-controller/arm-gic.h>
   90 
   91     aoss_qmp: qmp@c300000 {
   92       compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
   93       reg = <0x0c300000 0x100000>;
   94       interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
   95       mboxes = <&apss_shared 0>;
   96 
   97       #clock-cells = <0>;
   98 
   99       cx_cdev: cx {
  100         #cooling-cells = <2>;
  101       };
  102 
  103       mx_cdev: mx {
  104         #cooling-cells = <2>;
  105       };
  106     };
  107 ...

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sys/contrib/device-tree/Bindings/soc/qcom/qcom,aoss-qmp.yaml