qcom,gsbi.yaml

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    1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/soc/qcom/qcom,gsbi.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Qualcomm General Serial Bus Interface (GSBI)
    8 
    9 maintainers:
   10   - Andy Gross <agross@kernel.org>
   11   - Bjorn Andersson <bjorn.andersson@linaro.org>
   12   - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
   13 
   14 description:
   15   The GSBI controller is modeled as a node with zero or more child nodes, each
   16   representing a serial sub-node device that is mux'd as part of the GSBI
   17   configuration settings.  The mode setting will govern the input/output mode
   18   of the 4 GSBI IOs.
   19 
   20   A GSBI controller node can contain 0 or more child nodes representing serial
   21   devices.  These serial devices can be a QCOM UART, I2C controller, spi
   22   controller, or some combination of aforementioned devices.
   23 
   24 properties:
   25   compatible:
   26     const: qcom,gsbi-v1.0.0
   27 
   28   '#address-cells':
   29     const: 1
   30 
   31   cell-index:
   32     $ref: /schemas/types.yaml#/definitions/uint32
   33     description:
   34       The GSBI index.
   35 
   36   clocks:
   37     maxItems: 1
   38 
   39   clock-names:
   40     const: iface
   41 
   42   qcom,crci:
   43     $ref: /schemas/types.yaml#/definitions/uint32
   44     description:
   45       CRCI MUX value for QUP CRCI ports.  Please reference
   46       include/dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
   47 
   48   qcom,mode:
   49     $ref: /schemas/types.yaml#/definitions/uint32
   50     description:
   51       MUX value for configuration of the serial interface.  Please reference
   52       include/dt-bindings/soc/qcom,gsbi.h for valid mux values.
   53 
   54   '#size-cells':
   55     const: 1
   56 
   57   syscon-tcsr:
   58     $ref: /schemas/types.yaml#/definitions/phandle
   59     description:
   60       Phandle of TCSR syscon node.Required if child uses dma.
   61 
   62   ranges: true
   63 
   64   reg:
   65     maxItems: 1
   66 
   67 patternProperties:
   68   "spi@[0-9a-f]+$":
   69     type: object
   70     $ref: /schemas/spi/qcom,spi-qup.yaml#
   71 
   72   "i2c@[0-9a-f]+$":
   73     type: object
   74     $ref: /schemas/i2c/qcom,i2c-qup.yaml#
   75 
   76   "serial@[0-9a-f]+$":
   77     type: object
   78     $ref: /schemas/serial/qcom,msm-uartdm.yaml#
   79 
   80 required:
   81   - compatible
   82   - cell-index
   83   - clocks
   84   - clock-names
   85   - qcom,mode
   86   - reg
   87 
   88 additionalProperties: false
   89 
   90 examples:
   91   - |
   92     #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   93     #include <dt-bindings/interrupt-controller/arm-gic.h>
   94     #include <dt-bindings/soc/qcom,gsbi.h>
   95 
   96     gsbi@12440000 {
   97         compatible = "qcom,gsbi-v1.0.0";
   98         reg = <0x12440000 0x100>;
   99         cell-index = <1>;
  100         clocks = <&gcc GSBI1_H_CLK>;
  101         clock-names = "iface";
  102         #address-cells = <1>;
  103         #size-cells = <1>;
  104         ranges;
  105 
  106         syscon-tcsr = <&tcsr>;
  107         qcom,mode = <GSBI_PROT_I2C_UART>;
  108 
  109         serial@12450000 {
  110             compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  111             reg = <0x12450000 0x100>,
  112                   <0x12400000 0x03>;
  113             interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
  114             clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
  115             clock-names = "core", "iface";
  116         };
  117 
  118         i2c@12460000 {
  119             compatible = "qcom,i2c-qup-v1.1.1";
  120             reg = <0x12460000 0x1000>;
  121             pinctrl-0 = <&i2c1_pins>;
  122             pinctrl-1 = <&i2c1_pins_sleep>;
  123             pinctrl-names = "default", "sleep";
  124             interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
  125             clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
  126             clock-names = "core", "iface";
  127             #address-cells = <1>;
  128             #size-cells = <0>;
  129 
  130             status = "disabled"; /* UART chosen */
  131         };
  132     };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/soc/qcom/qcom,gsbi.yaml

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sys/contrib/device-tree/Bindings/soc/qcom/qcom,gsbi.yaml