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     1 Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
    2 
    3 The Freescale S/PDIF audio block is a stereo transceiver that allows the
    4 processor to receive and transmit digital audio via an coaxial cable or
    5 a fibre cable.
    6 
    7 Required properties:
    8 
    9   - compatible          : Compatible list, should contain one of the following
   10                           compatibles:
   11                           "fsl,imx35-spdif",
   12                           "fsl,vf610-spdif",
   13                           "fsl,imx6sx-spdif",
   14 
   15   - reg                 : Offset and length of the register set for the device.
   16 
   17   - interrupts          : Contains the spdif interrupt.
   18 
   19   - dmas                : Generic dma devicetree binding as described in
   20                           Documentation/devicetree/bindings/dma/dma.txt.
   21 
   22   - dma-names           : Two dmas have to be defined, "tx" and "rx".
   23 
   24   - clocks              : Contains an entry for each entry in clock-names.
   25 
   26   - clock-names         : Includes the following entries:
   27         "core"            The core clock of spdif controller.
   28         "rxtx<0-7>"       Clock source list for tx and rx clock.
   29                           This clock list should be identical to the source
   30                           list connecting to the spdif clock mux in "SPDIF
   31                           Transceiver Clock Diagram" of SoC reference manual.
   32                           It can also be referred to TxClk_Source bit of
   33                           register SPDIF_STC.
   34         "spba"            The spba clock is required when SPDIF is placed as a
   35                           bus slave of the Shared Peripheral Bus and when two
   36                           or more bus masters (CPU, DMA or DSP) try to access
   37                           it. This property is optional depending on the SoC
   38                           design.
   39 
   40 Optional properties:
   41 
   42    - big-endian         : If this property is absent, the native endian mode
   43                           will be in use as default, or the big endian mode
   44                           will be in use for all the device registers.
   45 
   46 Example:
   47 
   48 spdif: spdif@2004000 {
   49         compatible = "fsl,imx35-spdif";
   50         reg = <0x02004000 0x4000>;
   51         interrupts = <0 52 0x04>;
   52         dmas = <&sdma 14 18 0>,
   53                <&sdma 15 18 0>;
   54         dma-names = "rx", "tx";
   55 
   56         clocks = <&clks 197>, <&clks 3>,
   57                <&clks 197>, <&clks 107>,
   58                <&clks 0>, <&clks 118>,
   59                <&clks 62>, <&clks 139>,
   60                <&clks 0>;
   61         clock-names = "core", "rxtx0",
   62                 "rxtx1", "rxtx2",
   63                 "rxtx3", "rxtx4",
   64                 "rxtx5", "rxtx6",
   65                 "rxtx7";
   66 
   67         big-endian;
   68 };
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