1 * Freescale Quad Serial Peripheral Interface(QuadSPI)
2
3 Required properties:
4 - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
5 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
6 "fsl,ls1021a-qspi", "fsl,ls2080a-qspi"
7 or
8 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
9 - reg : the first contains the register location and length,
10 the second contains the memory mapping address and length
11 - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
12 - interrupts : Should contain the interrupt for the device
13 - clocks : The clocks needed by the QuadSPI controller
14 - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi".
15
16 Required SPI slave node properties:
17 - reg: There are two buses (A and B) with two chip selects each.
18 This encodes to which bus and CS the flash is connected:
19 <0>: Bus A, CS 0
20 <1>: Bus A, CS 1
21 <2>: Bus B, CS 0
22 <3>: Bus B, CS 1
23
24 Example:
25
26 qspi0: quadspi@40044000 {
27 compatible = "fsl,vf610-qspi";
28 reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
29 reg-names = "QuadSPI", "QuadSPI-memory";
30 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
31 clocks = <&clks VF610_CLK_QSPI0_EN>,
32 <&clks VF610_CLK_QSPI0>;
33 clock-names = "qspi_en", "qspi";
34
35 flash0: s25fl128s@0 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "spansion,s25fl128s", "jedec,spi-nor";
39 spi-max-frequency = <50000000>;
40 reg = <0>;
41 };
42 };
43
44 Example showing the usage of two SPI NOR devices on bus A:
45
46 &qspi2 {
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_qspi2>;
49 status = "okay";
50
51 flash0: n25q256a@0 {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 compatible = "micron,n25q256a", "jedec,spi-nor";
55 spi-max-frequency = <29000000>;
56 reg = <0>;
57 };
58
59 flash1: n25q256a@1 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "micron,n25q256a", "jedec,spi-nor";
63 spi-max-frequency = <29000000>;
64 reg = <1>;
65 };
66 };
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