spi-orion.txt

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    1 Marvell Orion SPI device
    2 
    3 Required properties:
    4 - compatible : should be on of the following:
    5     - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs
    6     - "marvell,armada-370-spi", for the Armada 370 SoCs
    7     - "marvell,armada-375-spi", for the Armada 375 SoCs
    8     - "marvell,armada-380-spi", for the Armada 38x SoCs
    9     - "marvell,armada-390-spi", for the Armada 39x SoCs
   10     - "marvell,armada-xp-spi", for the Armada XP SoCs
   11 - reg : offset and length of the register set for the device.
   12         This property can optionally have additional entries to configure
   13         the SPI direct access mode that some of the Marvell SoCs support
   14         additionally to the normal indirect access (PIO) mode. The values
   15         for the MBus "target" and "attribute" are defined in the Marvell
   16         SoC "Functional Specifications" Manual in the chapter "Marvell
   17         Core Processor Address Decoding".
   18         The eight register sets following the control registers refer to
   19         chip-select lines 0 through 7 respectively.
   20 - cell-index : Which of multiple SPI controllers is this.
   21 - clocks : pointers to the reference clocks for this device, the first
   22            one is the one used for the clock on the spi bus, the
   23            second one is optional and is the clock used for the
   24            functional part of the controller
   25 
   26 Optional properties:
   27 - interrupts : Is currently not used.
   28 - clock-names : names of used clocks, mandatory if the second clock is
   29                 used, the name must be "core", and "axi" (the latter
   30                 is only for Armada 7K/8K).
   31 
   32 
   33 Example:
   34        spi@10600 {
   35                compatible = "marvell,orion-spi";
   36                #address-cells = <1>;
   37                #size-cells = <0>;
   38                cell-index = <0>;
   39                reg = <0x10600 0x28>;
   40                interrupts = <23>;
   41        };
   42 
   43 Example with SPI direct mode support (optionally):
   44         spi0: spi@10600 {
   45                 compatible = "marvell,orion-spi";
   46                 #address-cells = <1>;
   47                 #size-cells = <0>;
   48                 cell-index = <0>;
   49                 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
   50                       <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
   51                       <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
   52                       <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
   53                       <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
   54                       <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
   55                       <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
   56                       <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
   57                       <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
   58                 interrupts = <23>;
   59         };
   60 
   61 To enable the direct mode, the board specific 'ranges' property in the
   62 'soc' node needs to add the entries for the desired SPI controllers
   63 and its chip-selects that are used in the direct mode instead of PIO
   64 mode. Here an example for this (SPI controller 0, device 1 and SPI
   65 controller 1, device 2 are used in direct mode. All other SPI device
   66 are used in the default indirect (PIO) mode):
   67         soc {
   68                 /*
   69                  * Enable the SPI direct access by configuring an entry
   70                  * here in the board-specific ranges property
   71                  */
   72                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000>, /* internal regs */
   73                          <MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>, /* BootROM       */
   74                          <MBUS_ID(0x01, 0x5e) 0 0 0xf1100000 0x10000>,  /* SPI0-DEV1 */
   75                          <MBUS_ID(0x01, 0x9a) 0 0 0xf1110000 0x10000>;  /* SPI1-DEV2 */
   76 
   77 For further information on the MBus bindings, please see the MBus
   78 DT documentation:
   79 Documentation/devicetree/bindings/bus/mvebu-mbus.txt

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sys/contrib/device-tree/Bindings/spi/spi-orion.txt