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     1 Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
    2 -------------------------------------------------------------------
    3 
    4 Required properties:
    5 - compatible            : Should be "xlnx,zynqmp-qspi-1.0".
    6 - reg                   : Physical base address and size of GQSPI registers map.
    7 - interrupts            : Property with a value describing the interrupt
    8                           number.
    9 - clock-names           : List of input clock names - "ref_clk", "pclk"
   10                           (See clock bindings for details).
   11 - clocks                : Clock phandles (see clock bindings for details).
   12 
   13 Optional properties:
   14 - num-cs                : Number of chip selects used.
   15 
   16 Example:
   17         qspi: spi@ff0f0000 {
   18                 compatible = "xlnx,zynqmp-qspi-1.0";
   19                 clock-names = "ref_clk", "pclk";
   20                 clocks = <&misc_clk &misc_clk>;
   21                 interrupts = <0 15 4>;
   22                 interrupt-parent = <&gic>;
   23                 num-cs = <1>;
   24                 reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>;
   25         };
Cache object: 0193733e3b5958bafd1d89ccc2f0b044 
 
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