1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
8
9 maintainers:
10 - Michal Simek <michal.simek@xilinx.com>
11
12 allOf:
13 - $ref: "spi-controller.yaml#"
14
15 properties:
16 compatible:
17 const: xlnx,zynqmp-qspi-1.0
18
19 reg:
20 maxItems: 2
21
22 interrupts:
23 maxItems: 1
24
25 clock-names:
26 items:
27 - const: ref_clk
28 - const: pclk
29
30 clocks:
31 maxItems: 2
32
33 required:
34 - compatible
35 - reg
36 - interrupts
37 - clock-names
38 - clocks
39
40 unevaluatedProperties: false
41
42 examples:
43 - |
44 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
45 soc {
46 #address-cells = <2>;
47 #size-cells = <2>;
48
49 qspi: spi@ff0f0000 {
50 compatible = "xlnx,zynqmp-qspi-1.0";
51 clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
52 clock-names = "ref_clk", "pclk";
53 interrupts = <0 15 4>;
54 interrupt-parent = <&gic>;
55 reg = <0x0 0xff0f0000 0x0 0x1000>,
56 <0x0 0xc0000000 0x0 0x8000000>;
57 };
58 };
Cache object: 8cdc66132d5ecb0249b1eeca1764f27a
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