1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright 2020 Linaro Ltd.
3 %YAML 1.2
4 ---
5 $id: http://devicetree.org/schemas/thermal/thermal-idle.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7
8 title: Thermal idle cooling device binding
9
10 maintainers:
11 - Daniel Lezcano <daniel.lezcano@linaro.org>
12
13 description: |
14 The thermal idle cooling device allows the system to passively
15 mitigate the temperature on the device by injecting idle cycles,
16 forcing it to cool down.
17
18 This binding describes the thermal idle node.
19
20 properties:
21 $nodename:
22 const: thermal-idle
23 description: |
24 A thermal-idle node describes the idle cooling device properties to
25 cool down efficiently the attached thermal zone.
26
27 '#cooling-cells':
28 const: 2
29 description: |
30 Must be 2, in order to specify minimum and maximum cooling state used in
31 the cooling-maps reference. The first cell is the minimum cooling state
32 and the second cell is the maximum cooling state requested.
33
34 duration-us:
35 description: |
36 The idle duration in microsecond the device should cool down.
37
38 exit-latency-us:
39 description: |
40 The exit latency constraint in microsecond for the injected idle state
41 for the device. It is the latency constraint to apply when selecting an
42 idle state from among all the present ones.
43
44 required:
45 - '#cooling-cells'
46
47 additionalProperties: false
48
49 examples:
50 - |
51 #include <dt-bindings/thermal/thermal.h>
52
53 // Example: Combining idle cooling device on big CPUs with cpufreq cooling device
54 cpus {
55 #address-cells = <2>;
56 #size-cells = <0>;
57
58 /* ... */
59
60 cpu_b0: cpu@100 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a72";
63 reg = <0x0 0x100>;
64 enable-method = "psci";
65 capacity-dmips-mhz = <1024>;
66 dynamic-power-coefficient = <436>;
67 #cooling-cells = <2>; /* min followed by max */
68 cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>;
69 thermal-idle {
70 #cooling-cells = <2>;
71 duration-us = <10000>;
72 exit-latency-us = <500>;
73 };
74 };
75
76 cpu_b1: cpu@101 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a72";
79 reg = <0x0 0x101>;
80 enable-method = "psci";
81 capacity-dmips-mhz = <1024>;
82 dynamic-power-coefficient = <436>;
83 #cooling-cells = <2>; /* min followed by max */
84 cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>;
85 thermal-idle {
86 #cooling-cells = <2>;
87 duration-us = <10000>;
88 exit-latency-us = <500>;
89 };
90 };
91
92 /* ... */
93
94 };
95
96 /* ... */
97
98 thermal_zones {
99 cpu_thermal: cpu {
100 polling-delay-passive = <100>;
101 polling-delay = <1000>;
102
103 /* ... */
104
105 trips {
106 cpu_alert0: cpu_alert0 {
107 temperature = <65000>;
108 hysteresis = <2000>;
109 type = "passive";
110 };
111
112 cpu_alert1: cpu_alert1 {
113 temperature = <70000>;
114 hysteresis = <2000>;
115 type = "passive";
116 };
117
118 cpu_alert2: cpu_alert2 {
119 temperature = <75000>;
120 hysteresis = <2000>;
121 type = "passive";
122 };
123
124 cpu_crit: cpu_crit {
125 temperature = <95000>;
126 hysteresis = <2000>;
127 type = "critical";
128 };
129 };
130
131 cooling-maps {
132 map0 {
133 trip = <&cpu_alert1>;
134 cooling-device = <&{/cpus/cpu@100/thermal-idle} 0 15 >,
135 <&{/cpus/cpu@101/thermal-idle} 0 15>;
136 };
137
138 map1 {
139 trip = <&cpu_alert2>;
140 cooling-device =
141 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
142 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
143 };
144 };
145 };
146 };
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