nvidia,tegra186-timer.yaml

Version: - FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10

    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#"
    5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
    6 
    7 title: NVIDIA Tegra186 timer
    8 
    9 maintainers:
   10   - Thierry Reding <treding@nvidia.com>
   11 
   12 description: >
   13   The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
   14   counter. Each NV timer selects its timing reference signal from the 1 MHz
   15   reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
   16   programmed to generate one-shot, periodic, or watchdog interrupts.
   17 
   18 
   19 properties:
   20   compatible:
   21     oneOf:
   22       - const: nvidia,tegra186-timer
   23         description: >
   24           The Tegra186 timer provides ten 29-bit timer counters.
   25       - const: nvidia,tegra234-timer
   26         description: >
   27           The Tegra234 timer provides sixteen 29-bit timer counters.
   28 
   29   reg:
   30     maxItems: 1
   31 
   32   interrupts: true
   33 
   34 allOf:
   35   - if:
   36       properties:
   37         compatible:
   38           contains:
   39             const: nvidia,tegra186-timer
   40     then:
   41       properties:
   42         interrupts:
   43           maxItems: 10
   44           description: >
   45             One per each timer channels 0 through 9.
   46 
   47   - if:
   48       properties:
   49         compatible:
   50           contains:
   51             const: nvidia,tegra234-timer
   52     then:
   53       properties:
   54         interrupts:
   55           maxItems: 16
   56           description: >
   57             One per each timer channels 0 through 15.
   58 
   59 required:
   60   - compatible
   61   - reg
   62   - interrupts
   63 
   64 additionalProperties: false
   65 
   66 examples:
   67   - |
   68     #include <dt-bindings/interrupt-controller/arm-gic.h>
   69     #include <dt-bindings/interrupt-controller/irq.h>
   70 
   71     timer@3010000 {
   72         compatible = "nvidia,tegra186-timer";
   73         reg = <0x03010000 0x000e0000>;
   74         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
   75                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
   76                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
   77                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
   78                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
   79                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
   80                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
   81                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
   82                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
   83                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
   84     };
   85 
   86   - |
   87     #include <dt-bindings/interrupt-controller/arm-gic.h>
   88     #include <dt-bindings/interrupt-controller/irq.h>
   89 
   90     timer@2080000 {
   91         compatible = "nvidia,tegra234-timer";
   92         reg = <0x02080000 0x00121000>;
   93         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
   94                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
   95                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
   96                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
   97                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
   98                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
   99                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  100                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  101                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  102                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  103                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
  104                      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  105                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  106                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
  107                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
  108                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  109     };

Cache object: 42ce107301cbb9c7bba1d99686befdac

[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.

FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/timer/nvidia,tegra186-timer.yaml

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/timer/nvidia,tegra186-timer.yaml