nvidia,tegra194-hte.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Tegra194 on chip generic hardware timestamping engine (HTE)
    8 
    9 maintainers:
   10   - Dipen Patel <dipenp@nvidia.com>
   11 
   12 description:
   13   Tegra SoC has two instances of generic hardware timestamping engines (GTE)
   14   known as GTE GPIO and GTE IRQ, which can monitor subset of GPIO and on chip
   15   IRQ lines for the state change respectively, upon detection it will record
   16   timestamp (taken from system counter) in its internal hardware FIFO. It has
   17   a bitmap array arranged in 32bit slices where each bit represent signal/line
   18   to enable or disable for the hardware timestamping. The GTE GPIO monitors
   19   GPIO lines from the AON (always on) GPIO controller.
   20 
   21 properties:
   22   compatible:
   23     enum:
   24       - nvidia,tegra194-gte-aon
   25       - nvidia,tegra194-gte-lic
   26 
   27   reg:
   28     maxItems: 1
   29 
   30   interrupts:
   31     maxItems: 1
   32 
   33   nvidia,int-threshold:
   34     $ref: /schemas/types.yaml#/definitions/uint32
   35     description:
   36       HTE device generates its interrupt based on this u32 FIFO threshold
   37       value. The recommended value is 1.
   38     minimum: 1
   39     maximum: 256
   40 
   41   nvidia,slices:
   42     $ref: /schemas/types.yaml#/definitions/uint32
   43     description:
   44       HTE lines are arranged in 32 bit slice where each bit represents different
   45       line/signal that it can enable/configure for the timestamp. It is u32
   46       property and depends on the HTE instance in the chip. The value 3 is for
   47       GPIO GTE and 11 for IRQ GTE.
   48     enum: [3, 11]
   49 
   50   '#timestamp-cells':
   51     description:
   52       This represents number of line id arguments as specified by the
   53       consumers. For the GTE IRQ, this is IRQ number as mentioned in the
   54       SoC technical reference manual. For the GTE GPIO, its value is same as
   55       mentioned in the nvidia GPIO device tree binding document.
   56     const: 1
   57 
   58 required:
   59   - compatible
   60   - reg
   61   - interrupts
   62   - nvidia,slices
   63   - "#timestamp-cells"
   64 
   65 additionalProperties: false
   66 
   67 examples:
   68   - |
   69     tegra_hte_aon: timestamp@c1e0000 {
   70               compatible = "nvidia,tegra194-gte-aon";
   71               reg = <0xc1e0000 0x10000>;
   72               interrupts = <0 13 0x4>;
   73               nvidia,int-threshold = <1>;
   74               nvidia,slices = <3>;
   75               #timestamp-cells = <1>;
   76     };
   77 
   78   - |
   79     tegra_hte_lic: timestamp@3aa0000 {
   80               compatible = "nvidia,tegra194-gte-lic";
   81               reg = <0x3aa0000 0x10000>;
   82               interrupts = <0 11 0x4>;
   83               nvidia,int-threshold = <1>;
   84               nvidia,slices = <11>;
   85               #timestamp-cells = <1>;
   86     };
   87 
   88 ...

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sys/contrib/device-tree/Bindings/timestamp/nvidia,tegra194-hte.yaml