samsung,exynos-ufs.yaml

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    1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Samsung SoC series UFS host controller Device Tree Bindings
    8 
    9 maintainers:
   10   - Alim Akhtar <alim.akhtar@samsung.com>
   11 
   12 description: |
   13   Each Samsung UFS host controller instance should have its own node.
   14 
   15 allOf:
   16   - $ref: ufs-common.yaml
   17 
   18 properties:
   19   compatible:
   20     enum:
   21       - samsung,exynos7-ufs
   22       - samsung,exynosautov9-ufs
   23       - samsung,exynosautov9-ufs-vh
   24       - tesla,fsd-ufs
   25 
   26   reg:
   27     items:
   28       - description: HCI register
   29       - description: vendor specific register
   30       - description: unipro register
   31       - description: UFS protector register
   32 
   33   reg-names:
   34     items:
   35       - const: hci
   36       - const: vs_hci
   37       - const: unipro
   38       - const: ufsp
   39 
   40   clocks:
   41     items:
   42       - description: ufs link core clock
   43       - description: unipro main clock
   44 
   45   clock-names:
   46     items:
   47       - const: core_clk
   48       - const: sclk_unipro_main
   49 
   50   phys:
   51     maxItems: 1
   52 
   53   phy-names:
   54     const: ufs-phy
   55 
   56   samsung,sysreg:
   57     $ref: '/schemas/types.yaml#/definitions/phandle-array'
   58     description: Should be phandle/offset pair. The phandle to the syscon node
   59                  which indicates the FSYSx sysreg interface and the offset of
   60                  the control register for UFS io coherency setting.
   61 
   62   dma-coherent: true
   63 
   64 required:
   65   - compatible
   66   - reg
   67   - phys
   68   - phy-names
   69   - clocks
   70   - clock-names
   71 
   72 unevaluatedProperties: false
   73 
   74 examples:
   75   - |
   76     #include <dt-bindings/interrupt-controller/arm-gic.h>
   77     #include <dt-bindings/clock/exynos7-clk.h>
   78 
   79     ufs: ufs@15570000 {
   80        compatible = "samsung,exynos7-ufs";
   81        reg = <0x15570000 0x100>,
   82              <0x15570100 0x100>,
   83              <0x15571000 0x200>,
   84              <0x15572000 0x300>;
   85        reg-names = "hci", "vs_hci", "unipro", "ufsp";
   86        interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
   87        clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
   88                 <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
   89        clock-names = "core_clk", "sclk_unipro_main";
   90        pinctrl-names = "default";
   91        pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
   92        phys = <&ufs_phy>;
   93        phy-names = "ufs-phy";
   94     };
   95 ...

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sys/contrib/device-tree/Bindings/ufs/samsung,exynos-ufs.yaml