dwc3-xilinx.txt

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    1 Xilinx SuperSpeed DWC3 USB SoC controller
    2 
    3 Required properties:
    4 - compatible:   May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
    5 - reg:          Base address and length of the register control block
    6 - clocks:       A list of phandles for the clocks listed in clock-names
    7 - clock-names:  Should contain the following:
    8   "bus_clk"      Master/Core clock, have to be >= 125 MHz for SS
    9                  operation and >= 60MHz for HS operation
   10 
   11   "ref_clk"      Clock source to core during PHY power down
   12 - resets:       A list of phandles for resets listed in reset-names
   13 - reset-names:
   14   "usb_crst"     USB core reset
   15   "usb_hibrst"   USB hibernation reset
   16   "usb_apbrst"   USB APB reset
   17 
   18 Required child node:
   19 A child node must exist to represent the core DWC3 IP block. The name of
   20 the node is not important. The content of the node is defined in dwc3.txt.
   21 
   22 Optional properties for snps,dwc3:
   23 - dma-coherent: Enable this flag if CCI is enabled in design. Adding this
   24                 flag configures Global SoC bus Configuration Register and
   25                 Xilinx USB 3.0 IP - USB coherency register to enable CCI.
   26 - interrupt-names: Should contain the following:
   27   "dwc_usb3"    USB gadget mode interrupts
   28   "otg"         USB OTG mode interrupts
   29   "hiber"       USB hibernation interrupts
   30 
   31 Example device node:
   32 
   33                 usb@0 {
   34                         #address-cells = <0x2>;
   35                         #size-cells = <0x1>;
   36                         compatible = "xlnx,zynqmp-dwc3";
   37                         reg = <0x0 0xff9d0000 0x0 0x100>;
   38                         clock-names = "bus_clk", "ref_clk";
   39                         clocks = <&clk125>, <&clk125>;
   40                         resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
   41                                  <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
   42                                  <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
   43                         reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
   44                         ranges;
   45 
   46                         dwc3@fe200000 {
   47                                 compatible = "snps,dwc3";
   48                                 reg = <0x0 0xfe200000 0x40000>;
   49                                 interrupt-names = "dwc_usb3", "otg", "hiber";
   50                                 interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
   51                                 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
   52                                 phy-names = "usb3-phy";
   53                                 dr_mode = "host";
   54                                 dma-coherent;
   55                         };
   56                 };

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