Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/usb/qcom,dwc3.yaml
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1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 %YAML 1.2 3 --- 4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 7 title: Qualcomm SuperSpeed DWC3 USB SoC controller 8 9 maintainers: 10 - Wesley Cheng <quic_wcheng@quicinc.com> 11 12 properties: 13 compatible: 14 items: 15 - enum: 16 - qcom,ipq4019-dwc3 17 - qcom,ipq6018-dwc3 18 - qcom,ipq8064-dwc3 19 - qcom,ipq8074-dwc3 20 - qcom,msm8953-dwc3 21 - qcom,msm8994-dwc3 22 - qcom,msm8996-dwc3 23 - qcom,msm8998-dwc3 24 - qcom,qcs404-dwc3 25 - qcom,sc7180-dwc3 26 - qcom,sc7280-dwc3 27 - qcom,sc8280xp-dwc3 28 - qcom,sdm660-dwc3 29 - qcom,sdm845-dwc3 30 - qcom,sdx55-dwc3 31 - qcom,sdx65-dwc3 32 - qcom,sm4250-dwc3 33 - qcom,sm6115-dwc3 34 - qcom,sm6125-dwc3 35 - qcom,sm6350-dwc3 36 - qcom,sm6375-dwc3 37 - qcom,sm8150-dwc3 38 - qcom,sm8250-dwc3 39 - qcom,sm8350-dwc3 40 - qcom,sm8450-dwc3 41 - const: qcom,dwc3 42 43 reg: 44 description: Offset and length of register set for QSCRATCH wrapper 45 maxItems: 1 46 47 "#address-cells": 48 enum: [ 1, 2 ] 49 50 "#size-cells": 51 enum: [ 1, 2 ] 52 53 ranges: true 54 55 power-domains: 56 description: specifies a phandle to PM domain provider node 57 maxItems: 1 58 59 clocks: 60 description: | 61 Several clocks are used, depending on the variant. Typical ones are:: 62 - cfg_noc:: System Config NOC clock. 63 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= 64 60MHz for HS operation. 65 - iface:: System bus AXI clock. 66 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low 67 power mode (U3). 68 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host 69 mode. Its frequency should be 19.2MHz. 70 minItems: 1 71 maxItems: 9 72 73 clock-names: 74 minItems: 1 75 maxItems: 9 76 77 assigned-clocks: 78 items: 79 - description: Phandle and clock specifier of MOCK_UTMI_CLK. 80 - description: Phandle and clock specifoer of MASTER_CLK. 81 82 assigned-clock-rates: 83 items: 84 - description: Must be 19.2MHz (19200000). 85 - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode. 86 resets: 87 maxItems: 1 88 89 interconnects: 90 maxItems: 2 91 92 interconnect-names: 93 items: 94 - const: usb-ddr 95 - const: apps-usb 96 97 interrupts: 98 minItems: 1 99 maxItems: 4 100 101 interrupt-names: 102 minItems: 1 103 maxItems: 4 104 105 qcom,select-utmi-as-pipe-clk: 106 description: 107 If present, disable USB3 pipe_clk requirement. 108 Used when dwc3 operates without SSPHY and only 109 HS/FS/LS modes are supported. 110 type: boolean 111 112 wakeup-source: true 113 114 # Required child node: 115 116 patternProperties: 117 "^usb@[0-9a-f]+$": 118 $ref: snps,dwc3.yaml# 119 120 properties: 121 wakeup-source: false 122 123 required: 124 - compatible 125 - reg 126 - "#address-cells" 127 - "#size-cells" 128 - ranges 129 - power-domains 130 - clocks 131 - clock-names 132 - interrupts 133 - interrupt-names 134 135 allOf: 136 - if: 137 properties: 138 compatible: 139 contains: 140 enum: 141 - qcom,ipq4019-dwc3 142 then: 143 properties: 144 clocks: 145 maxItems: 3 146 clock-names: 147 items: 148 - const: core 149 - const: sleep 150 - const: mock_utmi 151 152 - if: 153 properties: 154 compatible: 155 contains: 156 enum: 157 - qcom,ipq8064-dwc3 158 then: 159 properties: 160 clocks: 161 items: 162 - description: Master/Core clock, has to be >= 125 MHz 163 for SS operation and >= 60MHz for HS operation. 164 clock-names: 165 items: 166 - const: core 167 168 - if: 169 properties: 170 compatible: 171 contains: 172 enum: 173 - qcom,msm8953-dwc3 174 - qcom,msm8996-dwc3 175 - qcom,msm8998-dwc3 176 - qcom,sc7180-dwc3 177 - qcom,sc7280-dwc3 178 - qcom,sdm845-dwc3 179 - qcom,sdx55-dwc3 180 - qcom,sm6350-dwc3 181 then: 182 properties: 183 clocks: 184 maxItems: 5 185 clock-names: 186 items: 187 - const: cfg_noc 188 - const: core 189 - const: iface 190 - const: sleep 191 - const: mock_utmi 192 193 - if: 194 properties: 195 compatible: 196 contains: 197 enum: 198 - qcom,ipq6018-dwc3 199 then: 200 properties: 201 clocks: 202 minItems: 3 203 maxItems: 4 204 clock-names: 205 oneOf: 206 - items: 207 - const: core 208 - const: sleep 209 - const: mock_utmi 210 - items: 211 - const: cfg_noc 212 - const: core 213 - const: sleep 214 - const: mock_utmi 215 216 - if: 217 properties: 218 compatible: 219 contains: 220 enum: 221 - qcom,ipq8074-dwc3 222 then: 223 properties: 224 clocks: 225 maxItems: 4 226 clock-names: 227 items: 228 - const: cfg_noc 229 - const: core 230 - const: sleep 231 - const: mock_utmi 232 233 - if: 234 properties: 235 compatible: 236 contains: 237 enum: 238 - qcom,msm8994-dwc3 239 - qcom,qcs404-dwc3 240 then: 241 properties: 242 clocks: 243 maxItems: 4 244 clock-names: 245 items: 246 - const: core 247 - const: iface 248 - const: sleep 249 - const: mock_utmi 250 251 - if: 252 properties: 253 compatible: 254 contains: 255 enum: 256 - qcom,sc8280xp-dwc3 257 then: 258 properties: 259 clocks: 260 maxItems: 9 261 clock-names: 262 items: 263 - const: cfg_noc 264 - const: core 265 - const: iface 266 - const: sleep 267 - const: mock_utmi 268 - const: noc_aggr 269 - const: noc_aggr_north 270 - const: noc_aggr_south 271 - const: noc_sys 272 273 - if: 274 properties: 275 compatible: 276 contains: 277 enum: 278 - qcom,sdm660-dwc3 279 then: 280 properties: 281 clocks: 282 minItems: 6 283 clock-names: 284 items: 285 - const: cfg_noc 286 - const: core 287 - const: iface 288 - const: sleep 289 - const: mock_utmi 290 - const: bus 291 292 - if: 293 properties: 294 compatible: 295 contains: 296 enum: 297 - qcom,sm6125-dwc3 298 - qcom,sm8150-dwc3 299 - qcom,sm8250-dwc3 300 - qcom,sm8450-dwc3 301 then: 302 properties: 303 clocks: 304 minItems: 6 305 clock-names: 306 items: 307 - const: cfg_noc 308 - const: core 309 - const: iface 310 - const: sleep 311 - const: mock_utmi 312 - const: xo 313 314 - if: 315 properties: 316 compatible: 317 contains: 318 enum: 319 - qcom,sm8350-dwc3 320 then: 321 properties: 322 clocks: 323 minItems: 5 324 maxItems: 6 325 clock-names: 326 minItems: 5 327 items: 328 - const: cfg_noc 329 - const: core 330 - const: iface 331 - const: sleep 332 - const: mock_utmi 333 - const: xo 334 335 - if: 336 properties: 337 compatible: 338 contains: 339 enum: 340 - qcom,ipq4019-dwc3 341 - qcom,ipq6018-dwc3 342 - qcom,ipq8064-dwc3 343 - qcom,ipq8074-dwc3 344 - qcom,msm8994-dwc3 345 - qcom,qcs404-dwc3 346 - qcom,sc7180-dwc3 347 - qcom,sdm845-dwc3 348 - qcom,sdx55-dwc3 349 - qcom,sdx65-dwc3 350 - qcom,sm4250-dwc3 351 - qcom,sm6115-dwc3 352 - qcom,sm6125-dwc3 353 - qcom,sm6350-dwc3 354 - qcom,sm8150-dwc3 355 - qcom,sm8250-dwc3 356 - qcom,sm8350-dwc3 357 - qcom,sm8450-dwc3 358 then: 359 properties: 360 interrupts: 361 items: 362 - description: The interrupt that is asserted 363 when a wakeup event is received on USB2 bus. 364 - description: The interrupt that is asserted 365 when a wakeup event is received on USB3 bus. 366 - description: Wakeup event on DM line. 367 - description: Wakeup event on DP line. 368 interrupt-names: 369 items: 370 - const: hs_phy_irq 371 - const: ss_phy_irq 372 - const: dm_hs_phy_irq 373 - const: dp_hs_phy_irq 374 375 - if: 376 properties: 377 compatible: 378 contains: 379 enum: 380 - qcom,msm8953-dwc3 381 - qcom,msm8996-dwc3 382 - qcom,msm8998-dwc3 383 then: 384 properties: 385 interrupts: 386 maxItems: 2 387 interrupt-names: 388 items: 389 - const: hs_phy_irq 390 - const: ss_phy_irq 391 392 - if: 393 properties: 394 compatible: 395 contains: 396 enum: 397 - qcom,sdm660-dwc3 398 then: 399 properties: 400 interrupts: 401 minItems: 1 402 maxItems: 2 403 interrupt-names: 404 minItems: 1 405 items: 406 - const: hs_phy_irq 407 - const: ss_phy_irq 408 409 - if: 410 properties: 411 compatible: 412 contains: 413 enum: 414 - qcom,sc7280-dwc3 415 then: 416 properties: 417 interrupts: 418 minItems: 3 419 maxItems: 4 420 interrupt-names: 421 minItems: 3 422 items: 423 - const: hs_phy_irq 424 - const: dp_hs_phy_irq 425 - const: dm_hs_phy_irq 426 - const: ss_phy_irq 427 428 - if: 429 properties: 430 compatible: 431 contains: 432 enum: 433 - qcom,sc8280xp-dwc3 434 then: 435 properties: 436 interrupts: 437 maxItems: 4 438 interrupt-names: 439 items: 440 - const: pwr_event 441 - const: dp_hs_phy_irq 442 - const: dm_hs_phy_irq 443 - const: ss_phy_irq 444 445 additionalProperties: false 446 447 examples: 448 - | 449 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 450 #include <dt-bindings/interrupt-controller/arm-gic.h> 451 #include <dt-bindings/interrupt-controller/irq.h> 452 soc { 453 #address-cells = <2>; 454 #size-cells = <2>; 455 456 usb@a6f8800 { 457 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 458 reg = <0 0x0a6f8800 0 0x400>; 459 460 #address-cells = <2>; 461 #size-cells = <2>; 462 ranges; 463 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 464 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 465 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 466 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 467 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 468 clock-names = "cfg_noc", 469 "core", 470 "iface", 471 "sleep", 472 "mock_utmi"; 473 474 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 475 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 476 assigned-clock-rates = <19200000>, <150000000>; 477 478 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 482 interrupt-names = "hs_phy_irq", "ss_phy_irq", 483 "dm_hs_phy_irq", "dp_hs_phy_irq"; 484 485 power-domains = <&gcc USB30_PRIM_GDSC>; 486 487 resets = <&gcc GCC_USB30_PRIM_BCR>; 488 489 usb@a600000 { 490 compatible = "snps,dwc3"; 491 reg = <0 0x0a600000 0 0xcd00>; 492 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 493 iommus = <&apps_smmu 0x740 0>; 494 snps,dis_u2_susphy_quirk; 495 snps,dis_enblslpm_quirk; 496 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 497 phy-names = "usb2-phy", "usb3-phy"; 498 }; 499 }; 500 };
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