rockchip,dwc3.yaml

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    1 # SPDX-License-Identifier: GPL-2.0
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Rockchip SuperSpeed DWC3 USB SoC controller
    8 
    9 maintainers:
   10   - Heiko Stuebner <heiko@sntech.de>
   11 
   12 description:
   13   The common content of the node is defined in snps,dwc3.yaml.
   14 
   15   Phy documentation is provided in the following places.
   16 
   17   USB2.0 PHY
   18   Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
   19 
   20   Type-C PHY
   21   Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
   22 
   23 allOf:
   24   - $ref: snps,dwc3.yaml#
   25 
   26 select:
   27   properties:
   28     compatible:
   29       contains:
   30         enum:
   31           - rockchip,rk3328-dwc3
   32           - rockchip,rk3399-dwc3
   33           - rockchip,rk3568-dwc3
   34   required:
   35     - compatible
   36 
   37 properties:
   38   compatible:
   39     items:
   40       - enum:
   41           - rockchip,rk3328-dwc3
   42           - rockchip,rk3399-dwc3
   43           - rockchip,rk3568-dwc3
   44       - const: snps,dwc3
   45 
   46   reg:
   47     maxItems: 1
   48 
   49   interrupts:
   50     maxItems: 1
   51 
   52   clocks:
   53     minItems: 3
   54     items:
   55       - description:
   56           Controller reference clock, must to be 24 MHz
   57       - description:
   58           Controller suspend clock, must to be 24 MHz or 32 KHz
   59       - description:
   60           Master/Core clock, must to be >= 62.5 MHz for SS
   61           operation and >= 30MHz for HS operation
   62       - description:
   63           Controller grf clock
   64 
   65   clock-names:
   66     minItems: 3
   67     items:
   68       - const: ref_clk
   69       - const: suspend_clk
   70       - const: bus_clk
   71       - const: grf_clk
   72 
   73   power-domains:
   74     maxItems: 1
   75 
   76   resets:
   77     maxItems: 1
   78 
   79   reset-names:
   80     const: usb3-otg
   81 
   82 unevaluatedProperties: false
   83 
   84 required:
   85   - compatible
   86   - reg
   87   - interrupts
   88   - clocks
   89   - clock-names
   90 
   91 examples:
   92   - |
   93     #include <dt-bindings/clock/rk3399-cru.h>
   94     #include <dt-bindings/interrupt-controller/arm-gic.h>
   95 
   96     bus {
   97       #address-cells = <2>;
   98       #size-cells = <2>;
   99 
  100       usbdrd3_0: usb@fe800000 {
  101         compatible = "rockchip,rk3399-dwc3", "snps,dwc3";
  102         reg = <0x0 0xfe800000 0x0 0x100000>;
  103         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
  104         clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
  105                  <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
  106         clock-names = "ref_clk", "suspend_clk",
  107                       "bus_clk", "grf_clk";
  108         dr_mode = "otg";
  109       };
  110     };

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sys/contrib/device-tree/Bindings/usb/rockchip,dwc3.yaml