The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/watchdog/realtek,otto-wdt.yaml

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    1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Realtek Otto watchdog timer
    8 
    9 maintainers:
   10   - Sander Vanheule <sander@svanheule.net>
   11 
   12 description: |
   13   The timer has two timeout phases. Both phases have a maximum duration of 32
   14   prescaled clock ticks, which is ca. 43s with a bus clock of 200MHz. The
   15   minimum duration of each phase is one tick. Each phase can trigger an
   16   interrupt, although the phase 2 interrupt will occur with the system reset.
   17   - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
   18   - Phase 2: Starts after phase 1 has timed out, and only serves to give the
   19     system some time to clean up, or notify others that it's going to reset.
   20     During this phase, pinging the WDT has no effect, and a reset is
   21     unavoidable, unless the WDT is disabled.
   22 
   23 allOf:
   24   - $ref: watchdog.yaml#
   25 
   26 properties:
   27   compatible:
   28     enum:
   29       - realtek,rtl8380-wdt
   30       - realtek,rtl8390-wdt
   31       - realtek,rtl9300-wdt
   32       - realtek,rtl9310-wdt
   33 
   34   reg:
   35     maxItems: 1
   36 
   37   clocks:
   38     maxItems: 1
   39 
   40   interrupts:
   41     items:
   42       - description: interrupt specifier for pretimeout
   43       - description: interrupt specifier for timeout
   44 
   45   interrupt-names:
   46     items:
   47       - const: phase1
   48       - const: phase2
   49 
   50   realtek,reset-mode:
   51     $ref: /schemas/types.yaml#/definitions/string
   52     description: |
   53       Specify how the system is reset after a timeout. Defaults to "cpu" if
   54       left unspecified.
   55     oneOf:
   56       - description: Reset the entire chip
   57         const: soc
   58       - description: |
   59           Reset the CPU and IPsec engine, but leave other peripherals untouched
   60         const: cpu
   61       - description: |
   62           Reset the execution pointer, but don't actually reset any hardware
   63         const: software
   64 
   65 required:
   66   - compatible
   67   - reg
   68   - clocks
   69   - interrupts
   70 
   71 unevaluatedProperties: false
   72 
   73 dependencies:
   74   interrupts: [ interrupt-names ]
   75 
   76 examples:
   77   - |
   78     watchdog: watchdog@3150 {
   79         compatible = "realtek,rtl8380-wdt";
   80         reg = <0x3150 0xc>;
   81 
   82         realtek,reset-mode = "soc";
   83 
   84         clocks = <&lxbus_clock>;
   85         timeout-sec = <20>;
   86 
   87         interrupt-parent = <&rtlintc>;
   88         interrupt-names = "phase1", "phase2";
   89         interrupts = <19>, <18>;
   90     };
   91 
   92 ...

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