The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/include/dt-bindings/clock/am3.h

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
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    1 /* SPDX-License-Identifier: GPL-2.0-only */
    2 /*
    3  * Copyright 2017 Texas Instruments, Inc.
    4  */
    5 #ifndef __DT_BINDINGS_CLK_AM3_H
    6 #define __DT_BINDINGS_CLK_AM3_H
    7 
    8 #define AM3_CLKCTRL_OFFSET      0x0
    9 #define AM3_CLKCTRL_INDEX(offset)       ((offset) - AM3_CLKCTRL_OFFSET)
   10 
   11 /* l4ls clocks */
   12 #define AM3_L4LS_CLKCTRL_OFFSET 0x38
   13 #define AM3_L4LS_CLKCTRL_INDEX(offset)  ((offset) - AM3_L4LS_CLKCTRL_OFFSET)
   14 #define AM3_L4LS_UART6_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x38)
   15 #define AM3_L4LS_MMC1_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x3c)
   16 #define AM3_L4LS_ELM_CLKCTRL    AM3_L4LS_CLKCTRL_INDEX(0x40)
   17 #define AM3_L4LS_I2C3_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x44)
   18 #define AM3_L4LS_I2C2_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x48)
   19 #define AM3_L4LS_SPI0_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x4c)
   20 #define AM3_L4LS_SPI1_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0x50)
   21 #define AM3_L4LS_L4_LS_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x60)
   22 #define AM3_L4LS_UART2_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x6c)
   23 #define AM3_L4LS_UART3_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x70)
   24 #define AM3_L4LS_UART4_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x74)
   25 #define AM3_L4LS_UART5_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x78)
   26 #define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c)
   27 #define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80)
   28 #define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84)
   29 #define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88)
   30 #define AM3_L4LS_RNG_CLKCTRL    AM3_L4LS_CLKCTRL_INDEX(0x90)
   31 #define AM3_L4LS_GPIO2_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0xac)
   32 #define AM3_L4LS_GPIO3_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0xb0)
   33 #define AM3_L4LS_GPIO4_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0xb4)
   34 #define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0)
   35 #define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4)
   36 #define AM3_L4LS_EPWMSS1_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0xcc)
   37 #define AM3_L4LS_EPWMSS0_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0xd4)
   38 #define AM3_L4LS_EPWMSS2_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0xd8)
   39 #define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec)
   40 #define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0)
   41 #define AM3_L4LS_MMC2_CLKCTRL   AM3_L4LS_CLKCTRL_INDEX(0xf4)
   42 #define AM3_L4LS_SPINLOCK_CLKCTRL       AM3_L4LS_CLKCTRL_INDEX(0x10c)
   43 #define AM3_L4LS_MAILBOX_CLKCTRL        AM3_L4LS_CLKCTRL_INDEX(0x110)
   44 #define AM3_L4LS_OCPWP_CLKCTRL  AM3_L4LS_CLKCTRL_INDEX(0x130)
   45 
   46 /* l3s clocks */
   47 #define AM3_L3S_CLKCTRL_OFFSET  0x1c
   48 #define AM3_L3S_CLKCTRL_INDEX(offset)   ((offset) - AM3_L3S_CLKCTRL_OFFSET)
   49 #define AM3_L3S_USB_OTG_HS_CLKCTRL      AM3_L3S_CLKCTRL_INDEX(0x1c)
   50 #define AM3_L3S_GPMC_CLKCTRL    AM3_L3S_CLKCTRL_INDEX(0x30)
   51 #define AM3_L3S_MCASP0_CLKCTRL  AM3_L3S_CLKCTRL_INDEX(0x34)
   52 #define AM3_L3S_MCASP1_CLKCTRL  AM3_L3S_CLKCTRL_INDEX(0x68)
   53 #define AM3_L3S_MMC3_CLKCTRL    AM3_L3S_CLKCTRL_INDEX(0xf8)
   54 
   55 /* l3 clocks */
   56 #define AM3_L3_CLKCTRL_OFFSET   0x24
   57 #define AM3_L3_CLKCTRL_INDEX(offset)    ((offset) - AM3_L3_CLKCTRL_OFFSET)
   58 #define AM3_L3_TPTC0_CLKCTRL    AM3_L3_CLKCTRL_INDEX(0x24)
   59 #define AM3_L3_EMIF_CLKCTRL     AM3_L3_CLKCTRL_INDEX(0x28)
   60 #define AM3_L3_OCMCRAM_CLKCTRL  AM3_L3_CLKCTRL_INDEX(0x2c)
   61 #define AM3_L3_AES_CLKCTRL      AM3_L3_CLKCTRL_INDEX(0x94)
   62 #define AM3_L3_SHAM_CLKCTRL     AM3_L3_CLKCTRL_INDEX(0xa0)
   63 #define AM3_L3_TPCC_CLKCTRL     AM3_L3_CLKCTRL_INDEX(0xbc)
   64 #define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc)
   65 #define AM3_L3_L3_MAIN_CLKCTRL  AM3_L3_CLKCTRL_INDEX(0xe0)
   66 #define AM3_L3_TPTC1_CLKCTRL    AM3_L3_CLKCTRL_INDEX(0xfc)
   67 #define AM3_L3_TPTC2_CLKCTRL    AM3_L3_CLKCTRL_INDEX(0x100)
   68 
   69 /* l4hs clocks */
   70 #define AM3_L4HS_CLKCTRL_OFFSET 0x120
   71 #define AM3_L4HS_CLKCTRL_INDEX(offset)  ((offset) - AM3_L4HS_CLKCTRL_OFFSET)
   72 #define AM3_L4HS_L4_HS_CLKCTRL  AM3_L4HS_CLKCTRL_INDEX(0x120)
   73 
   74 /* pruss_ocp clocks */
   75 #define AM3_PRUSS_OCP_CLKCTRL_OFFSET    0xe8
   76 #define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset)     ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
   77 #define AM3_PRUSS_OCP_PRUSS_CLKCTRL     AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
   78 
   79 /* cpsw_125mhz clocks */
   80 #define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14)
   81 
   82 /* lcdc clocks */
   83 #define AM3_LCDC_CLKCTRL_OFFSET 0x18
   84 #define AM3_LCDC_CLKCTRL_INDEX(offset)  ((offset) - AM3_LCDC_CLKCTRL_OFFSET)
   85 #define AM3_LCDC_LCDC_CLKCTRL   AM3_LCDC_CLKCTRL_INDEX(0x18)
   86 
   87 /* clk_24mhz clocks */
   88 #define AM3_CLK_24MHZ_CLKCTRL_OFFSET    0x14c
   89 #define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset)     ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
   90 #define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
   91 
   92 /* l4_wkup clocks */
   93 #define AM3_L4_WKUP_CONTROL_CLKCTRL     AM3_CLKCTRL_INDEX(0x4)
   94 #define AM3_L4_WKUP_GPIO1_CLKCTRL       AM3_CLKCTRL_INDEX(0x8)
   95 #define AM3_L4_WKUP_L4_WKUP_CLKCTRL     AM3_CLKCTRL_INDEX(0xc)
   96 #define AM3_L4_WKUP_UART1_CLKCTRL       AM3_CLKCTRL_INDEX(0xb4)
   97 #define AM3_L4_WKUP_I2C1_CLKCTRL        AM3_CLKCTRL_INDEX(0xb8)
   98 #define AM3_L4_WKUP_ADC_TSC_CLKCTRL     AM3_CLKCTRL_INDEX(0xbc)
   99 #define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL        AM3_CLKCTRL_INDEX(0xc0)
  100 #define AM3_L4_WKUP_TIMER1_CLKCTRL      AM3_CLKCTRL_INDEX(0xc4)
  101 #define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL        AM3_CLKCTRL_INDEX(0xc8)
  102 #define AM3_L4_WKUP_WD_TIMER2_CLKCTRL   AM3_CLKCTRL_INDEX(0xd4)
  103 
  104 /* l3_aon clocks */
  105 #define AM3_L3_AON_CLKCTRL_OFFSET       0x14
  106 #define AM3_L3_AON_CLKCTRL_INDEX(offset)        ((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
  107 #define AM3_L3_AON_DEBUGSS_CLKCTRL      AM3_L3_AON_CLKCTRL_INDEX(0x14)
  108 
  109 /* l4_wkup_aon clocks */
  110 #define AM3_L4_WKUP_AON_CLKCTRL_OFFSET  0xb0
  111 #define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset)   ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
  112 #define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
  113 
  114 /* mpu clocks */
  115 #define AM3_MPU_MPU_CLKCTRL     AM3_CLKCTRL_INDEX(0x4)
  116 
  117 /* l4_rtc clocks */
  118 #define AM3_L4_RTC_RTC_CLKCTRL  AM3_CLKCTRL_INDEX(0x0)
  119 
  120 /* gfx_l3 clocks */
  121 #define AM3_GFX_L3_GFX_CLKCTRL  AM3_CLKCTRL_INDEX(0x4)
  122 
  123 /* l4_cefuse clocks */
  124 #define AM3_L4_CEFUSE_CEFUSE_CLKCTRL    AM3_CLKCTRL_INDEX(0x20)
  125 
  126 #endif

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