The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/include/dt-bindings/clock/am4.h

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
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    1 /* SPDX-License-Identifier: GPL-2.0-only */
    2 /*
    3  * Copyright 2017 Texas Instruments, Inc.
    4  */
    5 #ifndef __DT_BINDINGS_CLK_AM4_H
    6 #define __DT_BINDINGS_CLK_AM4_H
    7 
    8 #define AM4_CLKCTRL_OFFSET      0x20
    9 #define AM4_CLKCTRL_INDEX(offset)       ((offset) - AM4_CLKCTRL_OFFSET)
   10 
   11 /* l3s_tsc clocks */
   12 #define AM4_L3S_TSC_CLKCTRL_OFFSET      0x120
   13 #define AM4_L3S_TSC_CLKCTRL_INDEX(offset)       ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET)
   14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL     AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
   15 
   16 /* l4_wkup_aon clocks */
   17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET  0x228
   18 #define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset)   ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET)
   19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
   20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL     AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
   21 
   22 /* l4_wkup clocks */
   23 #define AM4_L4_WKUP_CLKCTRL_OFFSET      0x220
   24 #define AM4_L4_WKUP_CLKCTRL_INDEX(offset)       ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET)
   25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL     AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
   26 #define AM4_L4_WKUP_TIMER1_CLKCTRL      AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
   27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL   AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
   28 #define AM4_L4_WKUP_I2C1_CLKCTRL        AM4_L4_WKUP_CLKCTRL_INDEX(0x340)
   29 #define AM4_L4_WKUP_UART1_CLKCTRL       AM4_L4_WKUP_CLKCTRL_INDEX(0x348)
   30 #define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL        AM4_L4_WKUP_CLKCTRL_INDEX(0x350)
   31 #define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL        AM4_L4_WKUP_CLKCTRL_INDEX(0x358)
   32 #define AM4_L4_WKUP_CONTROL_CLKCTRL     AM4_L4_WKUP_CLKCTRL_INDEX(0x360)
   33 #define AM4_L4_WKUP_GPIO1_CLKCTRL       AM4_L4_WKUP_CLKCTRL_INDEX(0x368)
   34 
   35 /* mpu clocks */
   36 #define AM4_MPU_MPU_CLKCTRL     AM4_CLKCTRL_INDEX(0x20)
   37 
   38 /* gfx_l3 clocks */
   39 #define AM4_GFX_L3_GFX_CLKCTRL  AM4_CLKCTRL_INDEX(0x20)
   40 
   41 /* l4_rtc clocks */
   42 #define AM4_L4_RTC_RTC_CLKCTRL  AM4_CLKCTRL_INDEX(0x20)
   43 
   44 /* l3 clocks */
   45 #define AM4_L3_L3_MAIN_CLKCTRL  AM4_CLKCTRL_INDEX(0x20)
   46 #define AM4_L3_AES_CLKCTRL      AM4_CLKCTRL_INDEX(0x28)
   47 #define AM4_L3_DES_CLKCTRL      AM4_CLKCTRL_INDEX(0x30)
   48 #define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
   49 #define AM4_L3_OCMCRAM_CLKCTRL  AM4_CLKCTRL_INDEX(0x50)
   50 #define AM4_L3_SHAM_CLKCTRL     AM4_CLKCTRL_INDEX(0x58)
   51 #define AM4_L3_TPCC_CLKCTRL     AM4_CLKCTRL_INDEX(0x78)
   52 #define AM4_L3_TPTC0_CLKCTRL    AM4_CLKCTRL_INDEX(0x80)
   53 #define AM4_L3_TPTC1_CLKCTRL    AM4_CLKCTRL_INDEX(0x88)
   54 #define AM4_L3_TPTC2_CLKCTRL    AM4_CLKCTRL_INDEX(0x90)
   55 #define AM4_L3_L4_HS_CLKCTRL    AM4_CLKCTRL_INDEX(0xa0)
   56 
   57 /* l3s clocks */
   58 #define AM4_L3S_CLKCTRL_OFFSET  0x68
   59 #define AM4_L3S_CLKCTRL_INDEX(offset)   ((offset) - AM4_L3S_CLKCTRL_OFFSET)
   60 #define AM4_L3S_VPFE0_CLKCTRL   AM4_L3S_CLKCTRL_INDEX(0x68)
   61 #define AM4_L3S_VPFE1_CLKCTRL   AM4_L3S_CLKCTRL_INDEX(0x70)
   62 #define AM4_L3S_GPMC_CLKCTRL    AM4_L3S_CLKCTRL_INDEX(0x220)
   63 #define AM4_L3S_ADC1_CLKCTRL    AM4_L3S_CLKCTRL_INDEX(0x230)
   64 #define AM4_L3S_MCASP0_CLKCTRL  AM4_L3S_CLKCTRL_INDEX(0x238)
   65 #define AM4_L3S_MCASP1_CLKCTRL  AM4_L3S_CLKCTRL_INDEX(0x240)
   66 #define AM4_L3S_MMC3_CLKCTRL    AM4_L3S_CLKCTRL_INDEX(0x248)
   67 #define AM4_L3S_QSPI_CLKCTRL    AM4_L3S_CLKCTRL_INDEX(0x258)
   68 #define AM4_L3S_USB_OTG_SS0_CLKCTRL     AM4_L3S_CLKCTRL_INDEX(0x260)
   69 #define AM4_L3S_USB_OTG_SS1_CLKCTRL     AM4_L3S_CLKCTRL_INDEX(0x268)
   70 
   71 /* pruss_ocp clocks */
   72 #define AM4_PRUSS_OCP_CLKCTRL_OFFSET    0x320
   73 #define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset)     ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET)
   74 #define AM4_PRUSS_OCP_PRUSS_CLKCTRL     AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320)
   75 
   76 /* l4ls clocks */
   77 #define AM4_L4LS_CLKCTRL_OFFSET 0x420
   78 #define AM4_L4LS_CLKCTRL_INDEX(offset)  ((offset) - AM4_L4LS_CLKCTRL_OFFSET)
   79 #define AM4_L4LS_L4_LS_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x420)
   80 #define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428)
   81 #define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430)
   82 #define AM4_L4LS_EPWMSS0_CLKCTRL        AM4_L4LS_CLKCTRL_INDEX(0x438)
   83 #define AM4_L4LS_EPWMSS1_CLKCTRL        AM4_L4LS_CLKCTRL_INDEX(0x440)
   84 #define AM4_L4LS_EPWMSS2_CLKCTRL        AM4_L4LS_CLKCTRL_INDEX(0x448)
   85 #define AM4_L4LS_EPWMSS3_CLKCTRL        AM4_L4LS_CLKCTRL_INDEX(0x450)
   86 #define AM4_L4LS_EPWMSS4_CLKCTRL        AM4_L4LS_CLKCTRL_INDEX(0x458)
   87 #define AM4_L4LS_EPWMSS5_CLKCTRL        AM4_L4LS_CLKCTRL_INDEX(0x460)
   88 #define AM4_L4LS_ELM_CLKCTRL    AM4_L4LS_CLKCTRL_INDEX(0x468)
   89 #define AM4_L4LS_GPIO2_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x478)
   90 #define AM4_L4LS_GPIO3_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x480)
   91 #define AM4_L4LS_GPIO4_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x488)
   92 #define AM4_L4LS_GPIO5_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x490)
   93 #define AM4_L4LS_GPIO6_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x498)
   94 #define AM4_L4LS_HDQ1W_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x4a0)
   95 #define AM4_L4LS_I2C2_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x4a8)
   96 #define AM4_L4LS_I2C3_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x4b0)
   97 #define AM4_L4LS_MAILBOX_CLKCTRL        AM4_L4LS_CLKCTRL_INDEX(0x4b8)
   98 #define AM4_L4LS_MMC1_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x4c0)
   99 #define AM4_L4LS_MMC2_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x4c8)
  100 #define AM4_L4LS_RNG_CLKCTRL    AM4_L4LS_CLKCTRL_INDEX(0x4e0)
  101 #define AM4_L4LS_SPI0_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x500)
  102 #define AM4_L4LS_SPI1_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x508)
  103 #define AM4_L4LS_SPI2_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x510)
  104 #define AM4_L4LS_SPI3_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x518)
  105 #define AM4_L4LS_SPI4_CLKCTRL   AM4_L4LS_CLKCTRL_INDEX(0x520)
  106 #define AM4_L4LS_SPINLOCK_CLKCTRL       AM4_L4LS_CLKCTRL_INDEX(0x528)
  107 #define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530)
  108 #define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538)
  109 #define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540)
  110 #define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548)
  111 #define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550)
  112 #define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558)
  113 #define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560)
  114 #define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568)
  115 #define AM4_L4LS_TIMER10_CLKCTRL        AM4_L4LS_CLKCTRL_INDEX(0x570)
  116 #define AM4_L4LS_TIMER11_CLKCTRL        AM4_L4LS_CLKCTRL_INDEX(0x578)
  117 #define AM4_L4LS_UART2_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x580)
  118 #define AM4_L4LS_UART3_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x588)
  119 #define AM4_L4LS_UART4_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x590)
  120 #define AM4_L4LS_UART5_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x598)
  121 #define AM4_L4LS_UART6_CLKCTRL  AM4_L4LS_CLKCTRL_INDEX(0x5a0)
  122 #define AM4_L4LS_OCP2SCP0_CLKCTRL       AM4_L4LS_CLKCTRL_INDEX(0x5b8)
  123 #define AM4_L4LS_OCP2SCP1_CLKCTRL       AM4_L4LS_CLKCTRL_INDEX(0x5c0)
  124 
  125 /* emif clocks */
  126 #define AM4_EMIF_CLKCTRL_OFFSET 0x720
  127 #define AM4_EMIF_CLKCTRL_INDEX(offset)  ((offset) - AM4_EMIF_CLKCTRL_OFFSET)
  128 #define AM4_EMIF_EMIF_CLKCTRL   AM4_EMIF_CLKCTRL_INDEX(0x720)
  129 
  130 /* dss clocks */
  131 #define AM4_DSS_CLKCTRL_OFFSET  0xa20
  132 #define AM4_DSS_CLKCTRL_INDEX(offset)   ((offset) - AM4_DSS_CLKCTRL_OFFSET)
  133 #define AM4_DSS_DSS_CORE_CLKCTRL        AM4_DSS_CLKCTRL_INDEX(0xa20)
  134 
  135 /* cpsw_125mhz clocks */
  136 #define AM4_CPSW_125MHZ_CLKCTRL_OFFSET  0xb20
  137 #define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset)   ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET)
  138 #define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20)
  139 
  140 #endif

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