The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/include/dt-bindings/clock/exynos5410.h

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    1 /* SPDX-License-Identifier: GPL-2.0 */
    2 /*
    3  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
    4  * Copyright (c) 2016 Krzysztof Kozlowski
    5  *
    6  * Device Tree binding constants for Exynos5421 clock controller.
    7  */
    8 
    9 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
   10 #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
   11 
   12 /* core clocks */
   13 #define CLK_FIN_PLL             1
   14 #define CLK_FOUT_APLL           2
   15 #define CLK_FOUT_CPLL           3
   16 #define CLK_FOUT_MPLL           4
   17 #define CLK_FOUT_BPLL           5
   18 #define CLK_FOUT_KPLL           6
   19 #define CLK_FOUT_EPLL           7
   20 
   21 /* gate for special clocks (sclk) */
   22 #define CLK_SCLK_UART0          128
   23 #define CLK_SCLK_UART1          129
   24 #define CLK_SCLK_UART2          130
   25 #define CLK_SCLK_UART3          131
   26 #define CLK_SCLK_MMC0           132
   27 #define CLK_SCLK_MMC1           133
   28 #define CLK_SCLK_MMC2           134
   29 #define CLK_SCLK_USBD300        150
   30 #define CLK_SCLK_USBD301        151
   31 #define CLK_SCLK_USBPHY300      152
   32 #define CLK_SCLK_USBPHY301      153
   33 #define CLK_SCLK_PWM            155
   34 
   35 /* gate clocks */
   36 #define CLK_UART0               257
   37 #define CLK_UART1               258
   38 #define CLK_UART2               259
   39 #define CLK_UART3               260
   40 #define CLK_I2C0                261
   41 #define CLK_I2C1                262
   42 #define CLK_I2C2                263
   43 #define CLK_I2C3                264
   44 #define CLK_USI0                265
   45 #define CLK_USI1                266
   46 #define CLK_USI2                267
   47 #define CLK_USI3                268
   48 #define CLK_TSADC               270
   49 #define CLK_PWM                 279
   50 #define CLK_MCT                 315
   51 #define CLK_WDT                 316
   52 #define CLK_RTC                 317
   53 #define CLK_TMU                 318
   54 #define CLK_MMC0                351
   55 #define CLK_MMC1                352
   56 #define CLK_MMC2                353
   57 #define CLK_PDMA0               362
   58 #define CLK_PDMA1               363
   59 #define CLK_USBH20              365
   60 #define CLK_USBD300             366
   61 #define CLK_USBD301             367
   62 #define CLK_SSS                 471
   63 
   64 #define CLK_NR_CLKS             512
   65 
   66 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */

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