Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/include/dt-bindings/clock/imx8ulp-clock.h
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1 /* SPDX-License-Identifier: GPL-2.0+ OR MIT */ 2 /* 3 * Copyright 2021 NXP 4 */ 5 6 #ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H 7 #define __DT_BINDINGS_CLOCK_IMX8ULP_H 8 9 #define IMX8ULP_CLK_DUMMY 0 10 11 /* CGC1 */ 12 #define IMX8ULP_CLK_SPLL2 5 13 #define IMX8ULP_CLK_SPLL3 6 14 #define IMX8ULP_CLK_A35_SEL 7 15 #define IMX8ULP_CLK_A35_DIV 8 16 #define IMX8ULP_CLK_SPLL2_PRE_SEL 9 17 #define IMX8ULP_CLK_SPLL3_PRE_SEL 10 18 #define IMX8ULP_CLK_SPLL3_PFD0 11 19 #define IMX8ULP_CLK_SPLL3_PFD1 12 20 #define IMX8ULP_CLK_SPLL3_PFD2 13 21 #define IMX8ULP_CLK_SPLL3_PFD3 14 22 #define IMX8ULP_CLK_SPLL3_PFD0_DIV1 15 23 #define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16 24 #define IMX8ULP_CLK_SPLL3_PFD1_DIV1 17 25 #define IMX8ULP_CLK_SPLL3_PFD1_DIV2 18 26 #define IMX8ULP_CLK_SPLL3_PFD2_DIV1 19 27 #define IMX8ULP_CLK_SPLL3_PFD2_DIV2 20 28 #define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21 29 #define IMX8ULP_CLK_SPLL3_PFD3_DIV2 22 30 #define IMX8ULP_CLK_NIC_SEL 23 31 #define IMX8ULP_CLK_NIC_AD_DIVPLAT 24 32 #define IMX8ULP_CLK_NIC_PER_DIVPLAT 25 33 #define IMX8ULP_CLK_XBAR_SEL 26 34 #define IMX8ULP_CLK_XBAR_AD_DIVPLAT 27 35 #define IMX8ULP_CLK_XBAR_DIVBUS 28 36 #define IMX8ULP_CLK_XBAR_AD_SLOW 29 37 #define IMX8ULP_CLK_SOSC_DIV1 30 38 #define IMX8ULP_CLK_SOSC_DIV2 31 39 #define IMX8ULP_CLK_SOSC_DIV3 32 40 #define IMX8ULP_CLK_FROSC_DIV1 33 41 #define IMX8ULP_CLK_FROSC_DIV2 34 42 #define IMX8ULP_CLK_FROSC_DIV3 35 43 #define IMX8ULP_CLK_SPLL3_VCODIV 36 44 #define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE 37 45 #define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 38 46 #define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE 39 47 #define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE 40 48 #define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE 41 49 #define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE 42 50 #define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE 43 51 #define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE 44 52 #define IMX8ULP_CLK_SOSC_DIV1_GATE 45 53 #define IMX8ULP_CLK_SOSC_DIV2_GATE 46 54 #define IMX8ULP_CLK_SOSC_DIV3_GATE 47 55 #define IMX8ULP_CLK_FROSC_DIV1_GATE 48 56 #define IMX8ULP_CLK_FROSC_DIV2_GATE 49 57 #define IMX8ULP_CLK_FROSC_DIV3_GATE 50 58 #define IMX8ULP_CLK_SAI4_SEL 51 59 #define IMX8ULP_CLK_SAI5_SEL 52 60 #define IMX8ULP_CLK_AUD_CLK1 53 61 #define IMX8ULP_CLK_ARM 54 62 #define IMX8ULP_CLK_ENET_TS_SEL 55 63 64 #define IMX8ULP_CLK_CGC1_END 56 65 66 /* CGC2 */ 67 #define IMX8ULP_CLK_PLL4_PRE_SEL 0 68 #define IMX8ULP_CLK_PLL4 1 69 #define IMX8ULP_CLK_PLL4_VCODIV 2 70 #define IMX8ULP_CLK_DDR_SEL 3 71 #define IMX8ULP_CLK_DDR_DIV 4 72 #define IMX8ULP_CLK_LPAV_AXI_SEL 5 73 #define IMX8ULP_CLK_LPAV_AXI_DIV 6 74 #define IMX8ULP_CLK_LPAV_AHB_DIV 7 75 #define IMX8ULP_CLK_LPAV_BUS_DIV 8 76 #define IMX8ULP_CLK_PLL4_PFD0 9 77 #define IMX8ULP_CLK_PLL4_PFD1 10 78 #define IMX8ULP_CLK_PLL4_PFD2 11 79 #define IMX8ULP_CLK_PLL4_PFD3 12 80 #define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE 13 81 #define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 14 82 #define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE 15 83 #define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE 16 84 #define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE 17 85 #define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE 18 86 #define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE 19 87 #define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE 20 88 #define IMX8ULP_CLK_PLL4_PFD0_DIV1 21 89 #define IMX8ULP_CLK_PLL4_PFD0_DIV2 22 90 #define IMX8ULP_CLK_PLL4_PFD1_DIV1 23 91 #define IMX8ULP_CLK_PLL4_PFD1_DIV2 24 92 #define IMX8ULP_CLK_PLL4_PFD2_DIV1 25 93 #define IMX8ULP_CLK_PLL4_PFD2_DIV2 26 94 #define IMX8ULP_CLK_PLL4_PFD3_DIV1 27 95 #define IMX8ULP_CLK_PLL4_PFD3_DIV2 28 96 #define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE 29 97 #define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE 30 98 #define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE 31 99 #define IMX8ULP_CLK_CGC2_SOSC_DIV1 32 100 #define IMX8ULP_CLK_CGC2_SOSC_DIV2 33 101 #define IMX8ULP_CLK_CGC2_SOSC_DIV3 34 102 #define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE 35 103 #define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE 36 104 #define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE 37 105 #define IMX8ULP_CLK_CGC2_FROSC_DIV1 38 106 #define IMX8ULP_CLK_CGC2_FROSC_DIV2 39 107 #define IMX8ULP_CLK_CGC2_FROSC_DIV3 40 108 #define IMX8ULP_CLK_AUD_CLK2 41 109 #define IMX8ULP_CLK_SAI6_SEL 42 110 #define IMX8ULP_CLK_SAI7_SEL 43 111 #define IMX8ULP_CLK_SPDIF_SEL 44 112 #define IMX8ULP_CLK_HIFI_SEL 45 113 #define IMX8ULP_CLK_HIFI_DIVCORE 46 114 #define IMX8ULP_CLK_HIFI_DIVPLAT 47 115 #define IMX8ULP_CLK_DSI_PHY_REF 48 116 117 #define IMX8ULP_CLK_CGC2_END 49 118 119 /* PCC3 */ 120 #define IMX8ULP_CLK_WDOG3 0 121 #define IMX8ULP_CLK_WDOG4 1 122 #define IMX8ULP_CLK_LPIT1 2 123 #define IMX8ULP_CLK_TPM4 3 124 #define IMX8ULP_CLK_TPM5 4 125 #define IMX8ULP_CLK_FLEXIO1 5 126 #define IMX8ULP_CLK_I3C2 6 127 #define IMX8ULP_CLK_LPI2C4 7 128 #define IMX8ULP_CLK_LPI2C5 8 129 #define IMX8ULP_CLK_LPUART4 9 130 #define IMX8ULP_CLK_LPUART5 10 131 #define IMX8ULP_CLK_LPSPI4 11 132 #define IMX8ULP_CLK_LPSPI5 12 133 #define IMX8ULP_CLK_DMA1_MP 13 134 #define IMX8ULP_CLK_DMA1_CH0 14 135 #define IMX8ULP_CLK_DMA1_CH1 15 136 #define IMX8ULP_CLK_DMA1_CH2 16 137 #define IMX8ULP_CLK_DMA1_CH3 17 138 #define IMX8ULP_CLK_DMA1_CH4 18 139 #define IMX8ULP_CLK_DMA1_CH5 19 140 #define IMX8ULP_CLK_DMA1_CH6 20 141 #define IMX8ULP_CLK_DMA1_CH7 21 142 #define IMX8ULP_CLK_DMA1_CH8 22 143 #define IMX8ULP_CLK_DMA1_CH9 23 144 #define IMX8ULP_CLK_DMA1_CH10 24 145 #define IMX8ULP_CLK_DMA1_CH11 25 146 #define IMX8ULP_CLK_DMA1_CH12 26 147 #define IMX8ULP_CLK_DMA1_CH13 27 148 #define IMX8ULP_CLK_DMA1_CH14 28 149 #define IMX8ULP_CLK_DMA1_CH15 29 150 #define IMX8ULP_CLK_DMA1_CH16 30 151 #define IMX8ULP_CLK_DMA1_CH17 31 152 #define IMX8ULP_CLK_DMA1_CH18 32 153 #define IMX8ULP_CLK_DMA1_CH19 33 154 #define IMX8ULP_CLK_DMA1_CH20 34 155 #define IMX8ULP_CLK_DMA1_CH21 35 156 #define IMX8ULP_CLK_DMA1_CH22 36 157 #define IMX8ULP_CLK_DMA1_CH23 37 158 #define IMX8ULP_CLK_DMA1_CH24 38 159 #define IMX8ULP_CLK_DMA1_CH25 39 160 #define IMX8ULP_CLK_DMA1_CH26 40 161 #define IMX8ULP_CLK_DMA1_CH27 41 162 #define IMX8ULP_CLK_DMA1_CH28 42 163 #define IMX8ULP_CLK_DMA1_CH29 43 164 #define IMX8ULP_CLK_DMA1_CH30 44 165 #define IMX8ULP_CLK_DMA1_CH31 45 166 #define IMX8ULP_CLK_MU3_A 46 167 #define IMX8ULP_CLK_MU0_B 47 168 169 #define IMX8ULP_CLK_PCC3_END 48 170 171 /* PCC4 */ 172 #define IMX8ULP_CLK_FLEXSPI2 0 173 #define IMX8ULP_CLK_TPM6 1 174 #define IMX8ULP_CLK_TPM7 2 175 #define IMX8ULP_CLK_LPI2C6 3 176 #define IMX8ULP_CLK_LPI2C7 4 177 #define IMX8ULP_CLK_LPUART6 5 178 #define IMX8ULP_CLK_LPUART7 6 179 #define IMX8ULP_CLK_SAI4 7 180 #define IMX8ULP_CLK_SAI5 8 181 #define IMX8ULP_CLK_PCTLE 9 182 #define IMX8ULP_CLK_PCTLF 10 183 #define IMX8ULP_CLK_USDHC0 11 184 #define IMX8ULP_CLK_USDHC1 12 185 #define IMX8ULP_CLK_USDHC2 13 186 #define IMX8ULP_CLK_USB0 14 187 #define IMX8ULP_CLK_USB0_PHY 15 188 #define IMX8ULP_CLK_USB1 16 189 #define IMX8ULP_CLK_USB1_PHY 17 190 #define IMX8ULP_CLK_USB_XBAR 18 191 #define IMX8ULP_CLK_ENET 19 192 #define IMX8ULP_CLK_SFA1 20 193 #define IMX8ULP_CLK_RGPIOE 21 194 #define IMX8ULP_CLK_RGPIOF 22 195 196 #define IMX8ULP_CLK_PCC4_END 23 197 198 /* PCC5 */ 199 #define IMX8ULP_CLK_TPM8 0 200 #define IMX8ULP_CLK_SAI6 1 201 #define IMX8ULP_CLK_SAI7 2 202 #define IMX8ULP_CLK_SPDIF 3 203 #define IMX8ULP_CLK_ISI 4 204 #define IMX8ULP_CLK_CSI_REGS 5 205 #define IMX8ULP_CLK_PCTLD 6 206 #define IMX8ULP_CLK_CSI 7 207 #define IMX8ULP_CLK_DSI 8 208 #define IMX8ULP_CLK_WDOG5 9 209 #define IMX8ULP_CLK_EPDC 10 210 #define IMX8ULP_CLK_PXP 11 211 #define IMX8ULP_CLK_SFA2 12 212 #define IMX8ULP_CLK_GPU2D 13 213 #define IMX8ULP_CLK_GPU3D 14 214 #define IMX8ULP_CLK_DC_NANO 15 215 #define IMX8ULP_CLK_CSI_CLK_UI 16 216 #define IMX8ULP_CLK_CSI_CLK_ESC 17 217 #define IMX8ULP_CLK_RGPIOD 18 218 #define IMX8ULP_CLK_DMA2_MP 19 219 #define IMX8ULP_CLK_DMA2_CH0 20 220 #define IMX8ULP_CLK_DMA2_CH1 21 221 #define IMX8ULP_CLK_DMA2_CH2 22 222 #define IMX8ULP_CLK_DMA2_CH3 23 223 #define IMX8ULP_CLK_DMA2_CH4 24 224 #define IMX8ULP_CLK_DMA2_CH5 25 225 #define IMX8ULP_CLK_DMA2_CH6 26 226 #define IMX8ULP_CLK_DMA2_CH7 27 227 #define IMX8ULP_CLK_DMA2_CH8 28 228 #define IMX8ULP_CLK_DMA2_CH9 29 229 #define IMX8ULP_CLK_DMA2_CH10 30 230 #define IMX8ULP_CLK_DMA2_CH11 31 231 #define IMX8ULP_CLK_DMA2_CH12 32 232 #define IMX8ULP_CLK_DMA2_CH13 33 233 #define IMX8ULP_CLK_DMA2_CH14 34 234 #define IMX8ULP_CLK_DMA2_CH15 35 235 #define IMX8ULP_CLK_DMA2_CH16 36 236 #define IMX8ULP_CLK_DMA2_CH17 37 237 #define IMX8ULP_CLK_DMA2_CH18 38 238 #define IMX8ULP_CLK_DMA2_CH19 39 239 #define IMX8ULP_CLK_DMA2_CH20 40 240 #define IMX8ULP_CLK_DMA2_CH21 41 241 #define IMX8ULP_CLK_DMA2_CH22 42 242 #define IMX8ULP_CLK_DMA2_CH23 43 243 #define IMX8ULP_CLK_DMA2_CH24 44 244 #define IMX8ULP_CLK_DMA2_CH25 45 245 #define IMX8ULP_CLK_DMA2_CH26 46 246 #define IMX8ULP_CLK_DMA2_CH27 47 247 #define IMX8ULP_CLK_DMA2_CH28 48 248 #define IMX8ULP_CLK_DMA2_CH29 49 249 #define IMX8ULP_CLK_DMA2_CH30 50 250 #define IMX8ULP_CLK_DMA2_CH31 51 251 #define IMX8ULP_CLK_MU2_B 52 252 #define IMX8ULP_CLK_MU3_B 53 253 #define IMX8ULP_CLK_AVD_SIM 54 254 #define IMX8ULP_CLK_DSI_TX_ESC 55 255 256 #define IMX8ULP_CLK_PCC5_END 56 257 258 #endif
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