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     1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
    2 /*
    3  * Daire McNamara,<daire.mcnamara@microchip.com>
    4  * Copyright (C) 2020-2022 Microchip Technology Inc.  All rights reserved.
    5  */
    6 
    7 #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
    8 #define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
    9 
   10 #define CLK_CPU         0
   11 #define CLK_AXI         1
   12 #define CLK_AHB         2
   13 
   14 #define CLK_ENVM        3
   15 #define CLK_MAC0        4
   16 #define CLK_MAC1        5
   17 #define CLK_MMC         6
   18 #define CLK_TIMER       7
   19 #define CLK_MMUART0     8
   20 #define CLK_MMUART1     9
   21 #define CLK_MMUART2     10
   22 #define CLK_MMUART3     11
   23 #define CLK_MMUART4     12
   24 #define CLK_SPI0        13
   25 #define CLK_SPI1        14
   26 #define CLK_I2C0        15
   27 #define CLK_I2C1        16
   28 #define CLK_CAN0        17
   29 #define CLK_CAN1        18
   30 #define CLK_USB         19
   31 #define CLK_RESERVED    20
   32 #define CLK_RTC         21
   33 #define CLK_QSPI        22
   34 #define CLK_GPIO0       23
   35 #define CLK_GPIO1       24
   36 #define CLK_GPIO2       25
   37 #define CLK_DDRC        26
   38 #define CLK_FIC0        27
   39 #define CLK_FIC1        28
   40 #define CLK_FIC2        29
   41 #define CLK_FIC3        30
   42 #define CLK_ATHENA      31
   43 #define CLK_CFM         32
   44 
   45 #define CLK_RTCREF      33
   46 #define CLK_MSSPLL      34
   47 
   48 #endif  /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */
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