1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Purna Chandra Mandal,<purna.mandal@microchip.com>
4 * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
5 */
6
7 #ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
8 #define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
9
10 /* clock output indices */
11 #define POSCCLK 0
12 #define FRCCLK 1
13 #define BFRCCLK 2
14 #define LPRCCLK 3
15 #define SOSCCLK 4
16 #define FRCDIVCLK 5
17 #define PLLCLK 6
18 #define SCLK 7
19 #define PB1CLK 8
20 #define PB2CLK 9
21 #define PB3CLK 10
22 #define PB4CLK 11
23 #define PB5CLK 12
24 #define PB6CLK 13
25 #define PB7CLK 14
26 #define REF1CLK 15
27 #define REF2CLK 16
28 #define REF3CLK 17
29 #define REF4CLK 18
30 #define REF5CLK 19
31 #define UPLLCLK 20
32 #define MAXCLKS 21
33
34 #endif /* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */
Cache object: dcd66530d71b2cb7f7cab1bc3d979cba
|