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     1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
    2 /*
    3  * Copyright (C) 2021 Nuvoton Technologies.
    4  * Author: Tomer Maimon <tomer.maimon@nuvoton.com>
    5  *
    6  * Device Tree binding constants for NPCM8XX clock controller.
    7  */
    8 
    9 #ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H
   10 #define __DT_BINDINGS_CLOCK_NPCM8XX_H
   11 
   12 #define NPCM8XX_CLK_CPU         0
   13 #define NPCM8XX_CLK_GFX_PIXEL   1
   14 #define NPCM8XX_CLK_MC          2
   15 #define NPCM8XX_CLK_ADC         3
   16 #define NPCM8XX_CLK_AHB         4
   17 #define NPCM8XX_CLK_TIMER       5
   18 #define NPCM8XX_CLK_UART        6
   19 #define NPCM8XX_CLK_UART2       7
   20 #define NPCM8XX_CLK_MMC         8
   21 #define NPCM8XX_CLK_SPI3        9
   22 #define NPCM8XX_CLK_PCI         10
   23 #define NPCM8XX_CLK_AXI         11
   24 #define NPCM8XX_CLK_APB4        12
   25 #define NPCM8XX_CLK_APB3        13
   26 #define NPCM8XX_CLK_APB2        14
   27 #define NPCM8XX_CLK_APB1        15
   28 #define NPCM8XX_CLK_APB5        16
   29 #define NPCM8XX_CLK_CLKOUT      17
   30 #define NPCM8XX_CLK_GFX         18
   31 #define NPCM8XX_CLK_SU          19
   32 #define NPCM8XX_CLK_SU48        20
   33 #define NPCM8XX_CLK_SDHC        21
   34 #define NPCM8XX_CLK_SPI0        22
   35 #define NPCM8XX_CLK_SPI1        23
   36 #define NPCM8XX_CLK_SPIX        24
   37 #define NPCM8XX_CLK_RG          25
   38 #define NPCM8XX_CLK_RCP         26
   39 #define NPCM8XX_CLK_PRE_ADC     27
   40 #define NPCM8XX_CLK_ATB         28
   41 #define NPCM8XX_CLK_PRE_CLK     29
   42 #define NPCM8XX_CLK_TH          30
   43 #define NPCM8XX_CLK_REFCLK      31
   44 #define NPCM8XX_CLK_SYSBYPCK    32
   45 #define NPCM8XX_CLK_MCBYPCK     33
   46 
   47 #define NPCM8XX_NUM_CLOCKS      (NPCM8XX_CLK_MCBYPCK + 1)
   48 
   49 #endif
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