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     1 /* SPDX-License-Identifier: GPL-2.0-only */
    2 /*
    3  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
    4  */
    5 
    6 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
    7 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
    8 
    9 #define DISP_CC_PLL0                            0
   10 #define DISP_CC_PLL0_OUT_EVEN                   1
   11 #define DISP_CC_MDSS_AHB_CLK                    2
   12 #define DISP_CC_MDSS_AHB_CLK_SRC                3
   13 #define DISP_CC_MDSS_BYTE0_CLK                  4
   14 #define DISP_CC_MDSS_BYTE0_CLK_SRC              5
   15 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC          6
   16 #define DISP_CC_MDSS_BYTE0_INTF_CLK             7
   17 #define DISP_CC_MDSS_DP_AUX_CLK                 8
   18 #define DISP_CC_MDSS_DP_AUX_CLK_SRC             9
   19 #define DISP_CC_MDSS_DP_CRYPTO_CLK              10
   20 #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC          11
   21 #define DISP_CC_MDSS_DP_LINK_CLK                12
   22 #define DISP_CC_MDSS_DP_LINK_CLK_SRC            13
   23 #define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC        14
   24 #define DISP_CC_MDSS_DP_LINK_INTF_CLK           15
   25 #define DISP_CC_MDSS_DP_PIXEL_CLK               16
   26 #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC           17
   27 #define DISP_CC_MDSS_ESC0_CLK                   18
   28 #define DISP_CC_MDSS_ESC0_CLK_SRC               19
   29 #define DISP_CC_MDSS_MDP_CLK                    20
   30 #define DISP_CC_MDSS_MDP_CLK_SRC                21
   31 #define DISP_CC_MDSS_MDP_LUT_CLK                22
   32 #define DISP_CC_MDSS_NON_GDSC_AHB_CLK           23
   33 #define DISP_CC_MDSS_PCLK0_CLK                  24
   34 #define DISP_CC_MDSS_PCLK0_CLK_SRC              25
   35 #define DISP_CC_MDSS_ROT_CLK                    26
   36 #define DISP_CC_MDSS_ROT_CLK_SRC                27
   37 #define DISP_CC_MDSS_RSCC_AHB_CLK               28
   38 #define DISP_CC_MDSS_RSCC_VSYNC_CLK             29
   39 #define DISP_CC_MDSS_VSYNC_CLK                  30
   40 #define DISP_CC_MDSS_VSYNC_CLK_SRC              31
   41 #define DISP_CC_XO_CLK                          32
   42 
   43 /* DISP_CC GDSCR */
   44 #define MDSS_GDSC                               0
   45 
   46 #endif
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