Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/include/dt-bindings/clock/qcom,gcc-msm8994.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 4 */ 5 6 7 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H 8 #define _DT_BINDINGS_CLK_MSM_GCC_8994_H 9 10 #define GPLL0_EARLY 0 11 #define GPLL0 1 12 #define GPLL4_EARLY 2 13 #define GPLL4 3 14 #define UFS_AXI_CLK_SRC 4 15 #define USB30_MASTER_CLK_SRC 5 16 #define BLSP1_QUP1_I2C_APPS_CLK_SRC 6 17 #define BLSP1_QUP1_SPI_APPS_CLK_SRC 7 18 #define BLSP1_QUP2_I2C_APPS_CLK_SRC 8 19 #define BLSP1_QUP2_SPI_APPS_CLK_SRC 9 20 #define BLSP1_QUP3_I2C_APPS_CLK_SRC 10 21 #define BLSP1_QUP3_SPI_APPS_CLK_SRC 11 22 #define BLSP1_QUP4_I2C_APPS_CLK_SRC 12 23 #define BLSP1_QUP4_SPI_APPS_CLK_SRC 13 24 #define BLSP1_QUP5_I2C_APPS_CLK_SRC 14 25 #define BLSP1_QUP5_SPI_APPS_CLK_SRC 15 26 #define BLSP1_QUP6_I2C_APPS_CLK_SRC 16 27 #define BLSP1_QUP6_SPI_APPS_CLK_SRC 17 28 #define BLSP1_UART1_APPS_CLK_SRC 18 29 #define BLSP1_UART2_APPS_CLK_SRC 19 30 #define BLSP1_UART3_APPS_CLK_SRC 20 31 #define BLSP1_UART4_APPS_CLK_SRC 21 32 #define BLSP1_UART5_APPS_CLK_SRC 22 33 #define BLSP1_UART6_APPS_CLK_SRC 23 34 #define BLSP2_QUP1_I2C_APPS_CLK_SRC 24 35 #define BLSP2_QUP1_SPI_APPS_CLK_SRC 25 36 #define BLSP2_QUP2_I2C_APPS_CLK_SRC 26 37 #define BLSP2_QUP2_SPI_APPS_CLK_SRC 27 38 #define BLSP2_QUP3_I2C_APPS_CLK_SRC 28 39 #define BLSP2_QUP3_SPI_APPS_CLK_SRC 29 40 #define BLSP2_QUP4_I2C_APPS_CLK_SRC 30 41 #define BLSP2_QUP4_SPI_APPS_CLK_SRC 31 42 #define BLSP2_QUP5_I2C_APPS_CLK_SRC 32 43 #define BLSP2_QUP5_SPI_APPS_CLK_SRC 33 44 #define BLSP2_QUP6_I2C_APPS_CLK_SRC 34 45 #define BLSP2_QUP6_SPI_APPS_CLK_SRC 35 46 #define BLSP2_UART1_APPS_CLK_SRC 36 47 #define BLSP2_UART2_APPS_CLK_SRC 37 48 #define BLSP2_UART3_APPS_CLK_SRC 38 49 #define BLSP2_UART4_APPS_CLK_SRC 39 50 #define BLSP2_UART5_APPS_CLK_SRC 40 51 #define BLSP2_UART6_APPS_CLK_SRC 41 52 #define GP1_CLK_SRC 42 53 #define GP2_CLK_SRC 43 54 #define GP3_CLK_SRC 44 55 #define PCIE_0_AUX_CLK_SRC 45 56 #define PCIE_0_PIPE_CLK_SRC 46 57 #define PCIE_1_AUX_CLK_SRC 47 58 #define PCIE_1_PIPE_CLK_SRC 48 59 #define PDM2_CLK_SRC 49 60 #define SDCC1_APPS_CLK_SRC 50 61 #define SDCC2_APPS_CLK_SRC 51 62 #define SDCC3_APPS_CLK_SRC 52 63 #define SDCC4_APPS_CLK_SRC 53 64 #define TSIF_REF_CLK_SRC 54 65 #define USB30_MOCK_UTMI_CLK_SRC 55 66 #define USB3_PHY_AUX_CLK_SRC 56 67 #define USB_HS_SYSTEM_CLK_SRC 57 68 #define GCC_BLSP1_AHB_CLK 58 69 #define GCC_BLSP1_QUP1_I2C_APPS_CLK 59 70 #define GCC_BLSP1_QUP1_SPI_APPS_CLK 60 71 #define GCC_BLSP1_QUP2_I2C_APPS_CLK 61 72 #define GCC_BLSP1_QUP2_SPI_APPS_CLK 62 73 #define GCC_BLSP1_QUP3_I2C_APPS_CLK 63 74 #define GCC_BLSP1_QUP3_SPI_APPS_CLK 64 75 #define GCC_BLSP1_QUP4_I2C_APPS_CLK 65 76 #define GCC_BLSP1_QUP4_SPI_APPS_CLK 66 77 #define GCC_BLSP1_QUP5_I2C_APPS_CLK 67 78 #define GCC_BLSP1_QUP5_SPI_APPS_CLK 68 79 #define GCC_BLSP1_QUP6_I2C_APPS_CLK 69 80 #define GCC_BLSP1_QUP6_SPI_APPS_CLK 70 81 #define GCC_BLSP1_UART1_APPS_CLK 71 82 #define GCC_BLSP1_UART2_APPS_CLK 72 83 #define GCC_BLSP1_UART3_APPS_CLK 73 84 #define GCC_BLSP1_UART4_APPS_CLK 74 85 #define GCC_BLSP1_UART5_APPS_CLK 75 86 #define GCC_BLSP1_UART6_APPS_CLK 76 87 #define GCC_BLSP2_AHB_CLK 77 88 #define GCC_BLSP2_QUP1_I2C_APPS_CLK 78 89 #define GCC_BLSP2_QUP1_SPI_APPS_CLK 79 90 #define GCC_BLSP2_QUP2_I2C_APPS_CLK 80 91 #define GCC_BLSP2_QUP2_SPI_APPS_CLK 81 92 #define GCC_BLSP2_QUP3_I2C_APPS_CLK 82 93 #define GCC_BLSP2_QUP3_SPI_APPS_CLK 83 94 #define GCC_BLSP2_QUP4_I2C_APPS_CLK 84 95 #define GCC_BLSP2_QUP4_SPI_APPS_CLK 85 96 #define GCC_BLSP2_QUP5_I2C_APPS_CLK 86 97 #define GCC_BLSP2_QUP5_SPI_APPS_CLK 87 98 #define GCC_BLSP2_QUP6_I2C_APPS_CLK 88 99 #define GCC_BLSP2_QUP6_SPI_APPS_CLK 89 100 #define GCC_BLSP2_UART1_APPS_CLK 90 101 #define GCC_BLSP2_UART2_APPS_CLK 91 102 #define GCC_BLSP2_UART3_APPS_CLK 92 103 #define GCC_BLSP2_UART4_APPS_CLK 93 104 #define GCC_BLSP2_UART5_APPS_CLK 94 105 #define GCC_BLSP2_UART6_APPS_CLK 95 106 #define GCC_GP1_CLK 96 107 #define GCC_GP2_CLK 97 108 #define GCC_GP3_CLK 98 109 #define GCC_PCIE_0_AUX_CLK 99 110 #define GCC_PCIE_0_PIPE_CLK 100 111 #define GCC_PCIE_1_AUX_CLK 101 112 #define GCC_PCIE_1_PIPE_CLK 102 113 #define GCC_PDM2_CLK 103 114 #define GCC_SDCC1_APPS_CLK 104 115 #define GCC_SDCC2_APPS_CLK 105 116 #define GCC_SDCC3_APPS_CLK 106 117 #define GCC_SDCC4_APPS_CLK 107 118 #define GCC_SYS_NOC_UFS_AXI_CLK 108 119 #define GCC_SYS_NOC_USB3_AXI_CLK 109 120 #define GCC_TSIF_REF_CLK 110 121 #define GCC_UFS_AXI_CLK 111 122 #define GCC_UFS_RX_CFG_CLK 112 123 #define GCC_UFS_TX_CFG_CLK 113 124 #define GCC_USB30_MASTER_CLK 114 125 #define GCC_USB30_MOCK_UTMI_CLK 115 126 #define GCC_USB3_PHY_AUX_CLK 116 127 #define GCC_USB_HS_SYSTEM_CLK 117 128 #define GCC_SDCC1_AHB_CLK 118 129 #define GCC_LPASS_Q6_AXI_CLK 119 130 #define GCC_MSS_Q6_BIMC_AXI_CLK 120 131 #define GCC_PCIE_0_CFG_AHB_CLK 121 132 #define GCC_PCIE_0_MSTR_AXI_CLK 122 133 #define GCC_PCIE_0_SLV_AXI_CLK 123 134 #define GCC_PCIE_1_CFG_AHB_CLK 124 135 #define GCC_PCIE_1_MSTR_AXI_CLK 125 136 #define GCC_PCIE_1_SLV_AXI_CLK 126 137 #define GCC_PDM_AHB_CLK 127 138 #define GCC_SDCC2_AHB_CLK 128 139 #define GCC_SDCC3_AHB_CLK 129 140 #define GCC_SDCC4_AHB_CLK 130 141 #define GCC_TSIF_AHB_CLK 131 142 #define GCC_UFS_AHB_CLK 132 143 #define GCC_UFS_RX_SYMBOL_0_CLK 133 144 #define GCC_UFS_RX_SYMBOL_1_CLK 134 145 #define GCC_UFS_TX_SYMBOL_0_CLK 135 146 #define GCC_UFS_TX_SYMBOL_1_CLK 136 147 #define GCC_USB2_HS_PHY_SLEEP_CLK 137 148 #define GCC_USB30_SLEEP_CLK 138 149 #define GCC_USB_HS_AHB_CLK 139 150 #define GCC_USB_PHY_CFG_AHB2PHY_CLK 140 151 #define CONFIG_NOC_CLK_SRC 141 152 #define PERIPH_NOC_CLK_SRC 142 153 #define SYSTEM_NOC_CLK_SRC 143 154 #define GPLL0_OUT_MMSSCC 144 155 #define GPLL0_OUT_MSSCC 145 156 #define PCIE_0_PHY_LDO 146 157 #define PCIE_1_PHY_LDO 147 158 #define UFS_PHY_LDO 148 159 #define USB_SS_PHY_LDO 149 160 #define GCC_BOOT_ROM_AHB_CLK 150 161 #define GCC_PRNG_AHB_CLK 151 162 #define GCC_USB3_PHY_PIPE_CLK 152 163 164 /* GDSCs */ 165 #define PCIE_GDSC 0 166 #define PCIE_0_GDSC 1 167 #define PCIE_1_GDSC 2 168 #define USB30_GDSC 3 169 #define UFS_GDSC 4 170 171 /* Resets */ 172 #define USB3_PHY_RESET 0 173 #define USB3PHY_PHY_RESET 1 174 #define PCIE_PHY_0_RESET 2 175 #define PCIE_PHY_1_RESET 3 176 #define QUSB2_PHY_RESET 4 177 #define MSS_RESET 5 178 179 #endif
Cache object: decc578844e5cf778b2e913cbf027c55
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