Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/include/dt-bindings/clock/qcom,gcc-sc8180x.h
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1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Linaro Ltd. 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H 8 #define _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H 9 10 #define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 11 #define GCC_AGGRE_UFS_CARD_AXI_CLK 1 12 #define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2 13 #define GCC_AGGRE_UFS_PHY_AXI_CLK 3 14 #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4 15 #define GCC_AGGRE_USB3_MP_AXI_CLK 5 16 #define GCC_AGGRE_USB3_PRIM_AXI_CLK 6 17 #define GCC_AGGRE_USB3_SEC_AXI_CLK 7 18 #define GCC_BOOT_ROM_AHB_CLK 8 19 #define GCC_CAMERA_HF_AXI_CLK 9 20 #define GCC_CAMERA_SF_AXI_CLK 10 21 #define GCC_CFG_NOC_USB3_MP_AXI_CLK 11 22 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 23 #define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 24 #define GCC_CPUSS_AHB_CLK 14 25 #define GCC_CPUSS_AHB_CLK_SRC 15 26 #define GCC_CPUSS_RBCPR_CLK 16 27 #define GCC_DDRSS_GPU_AXI_CLK 17 28 #define GCC_DISP_HF_AXI_CLK 18 29 #define GCC_DISP_SF_AXI_CLK 19 30 #define GCC_EMAC_AXI_CLK 20 31 #define GCC_EMAC_PTP_CLK 21 32 #define GCC_EMAC_PTP_CLK_SRC 22 33 #define GCC_EMAC_RGMII_CLK 23 34 #define GCC_EMAC_RGMII_CLK_SRC 24 35 #define GCC_EMAC_SLV_AHB_CLK 25 36 #define GCC_GP1_CLK 26 37 #define GCC_GP1_CLK_SRC 27 38 #define GCC_GP2_CLK 28 39 #define GCC_GP2_CLK_SRC 29 40 #define GCC_GP3_CLK 30 41 #define GCC_GP3_CLK_SRC 31 42 #define GCC_GP4_CLK 32 43 #define GCC_GP4_CLK_SRC 33 44 #define GCC_GP5_CLK 34 45 #define GCC_GP5_CLK_SRC 35 46 #define GCC_GPU_GPLL0_CLK_SRC 36 47 #define GCC_GPU_GPLL0_DIV_CLK_SRC 37 48 #define GCC_GPU_MEMNOC_GFX_CLK 38 49 #define GCC_GPU_SNOC_DVM_GFX_CLK 39 50 #define GCC_NPU_AT_CLK 40 51 #define GCC_NPU_AXI_CLK 41 52 #define GCC_NPU_AXI_CLK_SRC 42 53 #define GCC_NPU_GPLL0_CLK_SRC 43 54 #define GCC_NPU_GPLL0_DIV_CLK_SRC 44 55 #define GCC_NPU_TRIG_CLK 45 56 #define GCC_PCIE0_PHY_REFGEN_CLK 46 57 #define GCC_PCIE1_PHY_REFGEN_CLK 47 58 #define GCC_PCIE2_PHY_REFGEN_CLK 48 59 #define GCC_PCIE3_PHY_REFGEN_CLK 49 60 #define GCC_PCIE_0_AUX_CLK 50 61 #define GCC_PCIE_0_AUX_CLK_SRC 51 62 #define GCC_PCIE_0_CFG_AHB_CLK 52 63 #define GCC_PCIE_0_MSTR_AXI_CLK 53 64 #define GCC_PCIE_0_PIPE_CLK 54 65 #define GCC_PCIE_0_SLV_AXI_CLK 55 66 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 56 67 #define GCC_PCIE_1_AUX_CLK 57 68 #define GCC_PCIE_1_AUX_CLK_SRC 58 69 #define GCC_PCIE_1_CFG_AHB_CLK 59 70 #define GCC_PCIE_1_MSTR_AXI_CLK 60 71 #define GCC_PCIE_1_PIPE_CLK 61 72 #define GCC_PCIE_1_SLV_AXI_CLK 62 73 #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 63 74 #define GCC_PCIE_2_AUX_CLK 64 75 #define GCC_PCIE_2_AUX_CLK_SRC 65 76 #define GCC_PCIE_2_CFG_AHB_CLK 66 77 #define GCC_PCIE_2_MSTR_AXI_CLK 67 78 #define GCC_PCIE_2_PIPE_CLK 68 79 #define GCC_PCIE_2_SLV_AXI_CLK 69 80 #define GCC_PCIE_2_SLV_Q2A_AXI_CLK 70 81 #define GCC_PCIE_3_AUX_CLK 71 82 #define GCC_PCIE_3_AUX_CLK_SRC 72 83 #define GCC_PCIE_3_CFG_AHB_CLK 73 84 #define GCC_PCIE_3_MSTR_AXI_CLK 74 85 #define GCC_PCIE_3_PIPE_CLK 75 86 #define GCC_PCIE_3_SLV_AXI_CLK 76 87 #define GCC_PCIE_3_SLV_Q2A_AXI_CLK 77 88 #define GCC_PCIE_PHY_AUX_CLK 78 89 #define GCC_PCIE_PHY_REFGEN_CLK_SRC 79 90 #define GCC_PDM2_CLK 80 91 #define GCC_PDM2_CLK_SRC 81 92 #define GCC_PDM_AHB_CLK 82 93 #define GCC_PDM_XO4_CLK 83 94 #define GCC_PRNG_AHB_CLK 84 95 #define GCC_QMIP_CAMERA_NRT_AHB_CLK 85 96 #define GCC_QMIP_CAMERA_RT_AHB_CLK 86 97 #define GCC_QMIP_DISP_AHB_CLK 87 98 #define GCC_QMIP_VIDEO_CVP_AHB_CLK 88 99 #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 89 100 #define GCC_QSPI_1_CNOC_PERIPH_AHB_CLK 90 101 #define GCC_QSPI_1_CORE_CLK 91 102 #define GCC_QSPI_1_CORE_CLK_SRC 92 103 #define GCC_QSPI_CNOC_PERIPH_AHB_CLK 93 104 #define GCC_QSPI_CORE_CLK 94 105 #define GCC_QSPI_CORE_CLK_SRC 95 106 #define GCC_QUPV3_WRAP0_S0_CLK 96 107 #define GCC_QUPV3_WRAP0_S0_CLK_SRC 97 108 #define GCC_QUPV3_WRAP0_S1_CLK 98 109 #define GCC_QUPV3_WRAP0_S1_CLK_SRC 99 110 #define GCC_QUPV3_WRAP0_S2_CLK 100 111 #define GCC_QUPV3_WRAP0_S2_CLK_SRC 101 112 #define GCC_QUPV3_WRAP0_S3_CLK 102 113 #define GCC_QUPV3_WRAP0_S3_CLK_SRC 103 114 #define GCC_QUPV3_WRAP0_S4_CLK 104 115 #define GCC_QUPV3_WRAP0_S4_CLK_SRC 105 116 #define GCC_QUPV3_WRAP0_S5_CLK 106 117 #define GCC_QUPV3_WRAP0_S5_CLK_SRC 107 118 #define GCC_QUPV3_WRAP0_S6_CLK 108 119 #define GCC_QUPV3_WRAP0_S6_CLK_SRC 109 120 #define GCC_QUPV3_WRAP0_S7_CLK 110 121 #define GCC_QUPV3_WRAP0_S7_CLK_SRC 111 122 #define GCC_QUPV3_WRAP1_S0_CLK 112 123 #define GCC_QUPV3_WRAP1_S0_CLK_SRC 113 124 #define GCC_QUPV3_WRAP1_S1_CLK 114 125 #define GCC_QUPV3_WRAP1_S1_CLK_SRC 115 126 #define GCC_QUPV3_WRAP1_S2_CLK 116 127 #define GCC_QUPV3_WRAP1_S2_CLK_SRC 117 128 #define GCC_QUPV3_WRAP1_S3_CLK 118 129 #define GCC_QUPV3_WRAP1_S3_CLK_SRC 119 130 #define GCC_QUPV3_WRAP1_S4_CLK 120 131 #define GCC_QUPV3_WRAP1_S4_CLK_SRC 121 132 #define GCC_QUPV3_WRAP1_S5_CLK 122 133 #define GCC_QUPV3_WRAP1_S5_CLK_SRC 123 134 #define GCC_QUPV3_WRAP2_S0_CLK 124 135 #define GCC_QUPV3_WRAP2_S0_CLK_SRC 125 136 #define GCC_QUPV3_WRAP2_S1_CLK 126 137 #define GCC_QUPV3_WRAP2_S1_CLK_SRC 127 138 #define GCC_QUPV3_WRAP2_S2_CLK 128 139 #define GCC_QUPV3_WRAP2_S2_CLK_SRC 129 140 #define GCC_QUPV3_WRAP2_S3_CLK 130 141 #define GCC_QUPV3_WRAP2_S3_CLK_SRC 131 142 #define GCC_QUPV3_WRAP2_S4_CLK 132 143 #define GCC_QUPV3_WRAP2_S4_CLK_SRC 133 144 #define GCC_QUPV3_WRAP2_S5_CLK 134 145 #define GCC_QUPV3_WRAP2_S5_CLK_SRC 135 146 #define GCC_QUPV3_WRAP_0_M_AHB_CLK 136 147 #define GCC_QUPV3_WRAP_0_S_AHB_CLK 137 148 #define GCC_QUPV3_WRAP_1_M_AHB_CLK 138 149 #define GCC_QUPV3_WRAP_1_S_AHB_CLK 139 150 #define GCC_QUPV3_WRAP_2_M_AHB_CLK 140 151 #define GCC_QUPV3_WRAP_2_S_AHB_CLK 141 152 #define GCC_SDCC2_AHB_CLK 142 153 #define GCC_SDCC2_APPS_CLK 143 154 #define GCC_SDCC2_APPS_CLK_SRC 144 155 #define GCC_SDCC4_AHB_CLK 145 156 #define GCC_SDCC4_APPS_CLK 146 157 #define GCC_SDCC4_APPS_CLK_SRC 147 158 #define GCC_SYS_NOC_CPUSS_AHB_CLK 148 159 #define GCC_TSIF_AHB_CLK 149 160 #define GCC_TSIF_INACTIVITY_TIMERS_CLK 150 161 #define GCC_TSIF_REF_CLK 151 162 #define GCC_TSIF_REF_CLK_SRC 152 163 #define GCC_UFS_CARD_2_AHB_CLK 153 164 #define GCC_UFS_CARD_2_AXI_CLK 154 165 #define GCC_UFS_CARD_2_AXI_CLK_SRC 155 166 #define GCC_UFS_CARD_2_ICE_CORE_CLK 156 167 #define GCC_UFS_CARD_2_ICE_CORE_CLK_SRC 157 168 #define GCC_UFS_CARD_2_PHY_AUX_CLK 158 169 #define GCC_UFS_CARD_2_PHY_AUX_CLK_SRC 159 170 #define GCC_UFS_CARD_2_RX_SYMBOL_0_CLK 160 171 #define GCC_UFS_CARD_2_RX_SYMBOL_1_CLK 161 172 #define GCC_UFS_CARD_2_TX_SYMBOL_0_CLK 162 173 #define GCC_UFS_CARD_2_UNIPRO_CORE_CLK 163 174 #define GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC 164 175 #define GCC_UFS_CARD_AHB_CLK 165 176 #define GCC_UFS_CARD_AXI_CLK 166 177 #define GCC_UFS_CARD_AXI_CLK_SRC 167 178 #define GCC_UFS_CARD_AXI_HW_CTL_CLK 168 179 #define GCC_UFS_CARD_ICE_CORE_CLK 169 180 #define GCC_UFS_CARD_ICE_CORE_CLK_SRC 170 181 #define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 171 182 #define GCC_UFS_CARD_PHY_AUX_CLK 172 183 #define GCC_UFS_CARD_PHY_AUX_CLK_SRC 173 184 #define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 174 185 #define GCC_UFS_CARD_RX_SYMBOL_0_CLK 175 186 #define GCC_UFS_CARD_RX_SYMBOL_1_CLK 176 187 #define GCC_UFS_CARD_TX_SYMBOL_0_CLK 177 188 #define GCC_UFS_CARD_UNIPRO_CORE_CLK 178 189 #define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 179 190 #define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 180 191 #define GCC_UFS_PHY_AHB_CLK 181 192 #define GCC_UFS_PHY_AXI_CLK 182 193 #define GCC_UFS_PHY_AXI_CLK_SRC 183 194 #define GCC_UFS_PHY_AXI_HW_CTL_CLK 184 195 #define GCC_UFS_PHY_ICE_CORE_CLK 185 196 #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 186 197 #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 187 198 #define GCC_UFS_PHY_PHY_AUX_CLK 188 199 #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 189 200 #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 190 201 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 191 202 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 192 203 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 193 204 #define GCC_UFS_PHY_UNIPRO_CORE_CLK 194 205 #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 195 206 #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 196 207 #define GCC_USB30_MP_MASTER_CLK 197 208 #define GCC_USB30_MP_MASTER_CLK_SRC 198 209 #define GCC_USB30_MP_MOCK_UTMI_CLK 199 210 #define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 200 211 #define GCC_USB30_MP_SLEEP_CLK 201 212 #define GCC_USB30_PRIM_MASTER_CLK 202 213 #define GCC_USB30_PRIM_MASTER_CLK_SRC 203 214 #define GCC_USB30_PRIM_MOCK_UTMI_CLK 204 215 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 205 216 #define GCC_USB30_PRIM_SLEEP_CLK 206 217 #define GCC_USB30_SEC_MASTER_CLK 207 218 #define GCC_USB30_SEC_MASTER_CLK_SRC 208 219 #define GCC_USB30_SEC_MOCK_UTMI_CLK 209 220 #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 210 221 #define GCC_USB30_SEC_SLEEP_CLK 211 222 #define GCC_USB3_MP_PHY_AUX_CLK 212 223 #define GCC_USB3_MP_PHY_AUX_CLK_SRC 213 224 #define GCC_USB3_MP_PHY_COM_AUX_CLK 214 225 #define GCC_USB3_MP_PHY_PIPE_0_CLK 215 226 #define GCC_USB3_MP_PHY_PIPE_1_CLK 216 227 #define GCC_USB3_PRIM_PHY_AUX_CLK 217 228 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 218 229 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 219 230 #define GCC_USB3_PRIM_PHY_PIPE_CLK 220 231 #define GCC_USB3_SEC_PHY_AUX_CLK 221 232 #define GCC_USB3_SEC_PHY_AUX_CLK_SRC 222 233 #define GCC_USB3_SEC_PHY_COM_AUX_CLK 223 234 #define GCC_USB3_SEC_PHY_PIPE_CLK 224 235 #define GCC_VIDEO_AXI0_CLK 225 236 #define GCC_VIDEO_AXI1_CLK 226 237 #define GCC_VIDEO_AXIC_CLK 227 238 #define GPLL0 228 239 #define GPLL0_OUT_EVEN 229 240 #define GPLL1 230 241 #define GPLL4 231 242 #define GPLL7 232 243 #define GCC_PCIE_0_CLKREF_CLK 233 244 #define GCC_PCIE_1_CLKREF_CLK 234 245 #define GCC_PCIE_2_CLKREF_CLK 235 246 #define GCC_PCIE_3_CLKREF_CLK 236 247 #define GCC_USB3_PRIM_CLKREF_CLK 237 248 #define GCC_USB3_SEC_CLKREF_CLK 238 249 250 #define GCC_EMAC_BCR 0 251 #define GCC_GPU_BCR 1 252 #define GCC_MMSS_BCR 2 253 #define GCC_NPU_BCR 3 254 #define GCC_PCIE_0_BCR 4 255 #define GCC_PCIE_0_PHY_BCR 5 256 #define GCC_PCIE_1_BCR 6 257 #define GCC_PCIE_1_PHY_BCR 7 258 #define GCC_PCIE_2_BCR 8 259 #define GCC_PCIE_2_PHY_BCR 9 260 #define GCC_PCIE_3_BCR 10 261 #define GCC_PCIE_3_PHY_BCR 11 262 #define GCC_PCIE_PHY_BCR 12 263 #define GCC_PDM_BCR 13 264 #define GCC_PRNG_BCR 14 265 #define GCC_QSPI_1_BCR 15 266 #define GCC_QSPI_BCR 16 267 #define GCC_QUPV3_WRAPPER_0_BCR 17 268 #define GCC_QUPV3_WRAPPER_1_BCR 18 269 #define GCC_QUPV3_WRAPPER_2_BCR 19 270 #define GCC_QUSB2PHY_5_BCR 20 271 #define GCC_QUSB2PHY_MP0_BCR 21 272 #define GCC_QUSB2PHY_MP1_BCR 22 273 #define GCC_QUSB2PHY_PRIM_BCR 23 274 #define GCC_QUSB2PHY_SEC_BCR 24 275 #define GCC_USB3_PHY_PRIM_SP0_BCR 25 276 #define GCC_USB3_PHY_PRIM_SP1_BCR 26 277 #define GCC_USB3_DP_PHY_PRIM_SP0_BCR 27 278 #define GCC_USB3_DP_PHY_PRIM_SP1_BCR 28 279 #define GCC_USB3_PHY_SEC_BCR 29 280 #define GCC_USB3PHY_PHY_SEC_BCR 30 281 #define GCC_SDCC2_BCR 31 282 #define GCC_SDCC4_BCR 32 283 #define GCC_TSIF_BCR 33 284 #define GCC_UFS_CARD_2_BCR 34 285 #define GCC_UFS_CARD_BCR 35 286 #define GCC_UFS_PHY_BCR 36 287 #define GCC_USB30_MP_BCR 37 288 #define GCC_USB30_PRIM_BCR 38 289 #define GCC_USB30_SEC_BCR 39 290 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 40 291 #define GCC_VIDEO_AXIC_CLK_BCR 41 292 #define GCC_VIDEO_AXI0_CLK_BCR 42 293 #define GCC_VIDEO_AXI1_CLK_BCR 43 294 #define GCC_USB3_DP_PHY_SEC_BCR 44 295 296 /* GCC GDSCRs */ 297 #define EMAC_GDSC 0 298 #define PCIE_0_GDSC 1 299 #define PCIE_1_GDSC 2 300 #define PCIE_2_GDSC 3 301 #define PCIE_3_GDSC 4 302 #define UFS_CARD_2_GDSC 5 303 #define UFS_CARD_GDSC 6 304 #define UFS_PHY_GDSC 7 305 #define USB30_MP_GDSC 8 306 #define USB30_PRIM_GDSC 9 307 #define USB30_SEC_GDSC 10 308 309 #endif
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