The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/include/dt-bindings/clock/qcom,gpucc-sm6350.h

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    1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
    2 /*
    3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
    4  * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
    5  */
    6 
    7 #ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6350_H
    8 #define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6350_H
    9 
   10 /* GPU_CC clocks */
   11 #define GPU_CC_PLL0                                             0
   12 #define GPU_CC_PLL1                                             1
   13 #define GPU_CC_ACD_AHB_CLK                                      2
   14 #define GPU_CC_ACD_CXO_CLK                                      3
   15 #define GPU_CC_AHB_CLK                                          4
   16 #define GPU_CC_CRC_AHB_CLK                                      5
   17 #define GPU_CC_CX_GFX3D_CLK                                     6
   18 #define GPU_CC_CX_GFX3D_SLV_CLK                                 7
   19 #define GPU_CC_CX_GMU_CLK                                       8
   20 #define GPU_CC_CX_SNOC_DVM_CLK                                  9
   21 #define GPU_CC_CXO_AON_CLK                                      10
   22 #define GPU_CC_CXO_CLK                                          11
   23 #define GPU_CC_GMU_CLK_SRC                                      12
   24 #define GPU_CC_GX_CXO_CLK                                       13
   25 #define GPU_CC_GX_GFX3D_CLK                                     14
   26 #define GPU_CC_GX_GFX3D_CLK_SRC                                 15
   27 #define GPU_CC_GX_GMU_CLK                                       16
   28 #define GPU_CC_GX_VSENSE_CLK                                    17
   29 
   30 /* CLK_HW */
   31 #define GPU_CC_CRC_DIV                                          0
   32 
   33 /* GDSCs */
   34 #define GPU_CX_GDSC                                             0
   35 #define GPU_GX_GDSC                                             1
   36 
   37 #endif

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