The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/include/dt-bindings/clock/qcom,mmcc-msm8994.h

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
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    1 /* SPDX-License-Identifier: GPL-2.0-only */
    2 /*
    3  * Copyright (c) 2020, Konrad Dybcio
    4  */
    5 
    6 #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8994_H
    7 #define _DT_BINDINGS_CLK_MSM_MMCC_8994_H
    8 
    9 /* Clocks */
   10 #define MMPLL0_EARLY                                    0
   11 #define MMPLL0_PLL                                              1
   12 #define MMPLL1_EARLY                                    2
   13 #define MMPLL1_PLL                                              3
   14 #define MMPLL3_EARLY                                    4
   15 #define MMPLL3_PLL                                              5
   16 #define MMPLL4_EARLY                                    6
   17 #define MMPLL4_PLL                                              7
   18 #define MMPLL5_EARLY                                    8
   19 #define MMPLL5_PLL                                              9
   20 #define AXI_CLK_SRC                                             10
   21 #define RBBMTIMER_CLK_SRC                               11
   22 #define PCLK0_CLK_SRC                                   12
   23 #define PCLK1_CLK_SRC                                   13
   24 #define MDP_CLK_SRC                                             14
   25 #define VSYNC_CLK_SRC                                   15
   26 #define BYTE0_CLK_SRC                                   16
   27 #define BYTE1_CLK_SRC                                   17
   28 #define ESC0_CLK_SRC                                    18
   29 #define ESC1_CLK_SRC                                    19
   30 #define MDSS_AHB_CLK                                    20
   31 #define MDSS_PCLK0_CLK                                  21
   32 #define MDSS_PCLK1_CLK                                  22
   33 #define MDSS_VSYNC_CLK                                  23
   34 #define MDSS_BYTE0_CLK                                  24
   35 #define MDSS_BYTE1_CLK                                  25
   36 #define MDSS_ESC0_CLK                                   26
   37 #define MDSS_ESC1_CLK                                   27
   38 #define CSI0_CLK_SRC                                    28
   39 #define CSI1_CLK_SRC                                    29
   40 #define CSI2_CLK_SRC                                    30
   41 #define CSI3_CLK_SRC                                    31
   42 #define VFE0_CLK_SRC                                    32
   43 #define VFE1_CLK_SRC                                    33
   44 #define CPP_CLK_SRC                                             34
   45 #define JPEG0_CLK_SRC                                   35
   46 #define JPEG1_CLK_SRC                                   36
   47 #define JPEG2_CLK_SRC                                   37
   48 #define CSI2PHYTIMER_CLK_SRC                    38
   49 #define FD_CORE_CLK_SRC                                 39
   50 #define OCMEMNOC_CLK_SRC                                40
   51 #define CCI_CLK_SRC                                             41
   52 #define MMSS_GP0_CLK_SRC                                42
   53 #define MMSS_GP1_CLK_SRC                                43
   54 #define JPEG_DMA_CLK_SRC                                44
   55 #define MCLK0_CLK_SRC                                   45
   56 #define MCLK1_CLK_SRC                                   46
   57 #define MCLK2_CLK_SRC                                   47
   58 #define MCLK3_CLK_SRC                                   48
   59 #define CSI0PHYTIMER_CLK_SRC                    49
   60 #define CSI1PHYTIMER_CLK_SRC                    50
   61 #define EXTPCLK_CLK_SRC                                 51
   62 #define HDMI_CLK_SRC                                    52
   63 #define CAMSS_AHB_CLK                                   53
   64 #define CAMSS_CCI_CCI_AHB_CLK                   54
   65 #define CAMSS_CCI_CCI_CLK                               55
   66 #define CAMSS_VFE_CPP_AHB_CLK                   56
   67 #define CAMSS_VFE_CPP_AXI_CLK                   57
   68 #define CAMSS_VFE_CPP_CLK                               58
   69 #define CAMSS_CSI0_AHB_CLK                              59
   70 #define CAMSS_CSI0_CLK                                  60
   71 #define CAMSS_CSI0PHY_CLK                               61
   72 #define CAMSS_CSI0PIX_CLK                               62
   73 #define CAMSS_CSI0RDI_CLK                               63
   74 #define CAMSS_CSI1_AHB_CLK                              64
   75 #define CAMSS_CSI1_CLK                                  65
   76 #define CAMSS_CSI1PHY_CLK                               66
   77 #define CAMSS_CSI1PIX_CLK                               67
   78 #define CAMSS_CSI1RDI_CLK                               68
   79 #define CAMSS_CSI2_AHB_CLK                              69
   80 #define CAMSS_CSI2_CLK                                  70
   81 #define CAMSS_CSI2PHY_CLK                               71
   82 #define CAMSS_CSI2PIX_CLK                               72
   83 #define CAMSS_CSI2RDI_CLK                               73
   84 #define CAMSS_CSI3_AHB_CLK                              74
   85 #define CAMSS_CSI3_CLK                                  75
   86 #define CAMSS_CSI3PHY_CLK                               76
   87 #define CAMSS_CSI3PIX_CLK                               77
   88 #define CAMSS_CSI3RDI_CLK                               78
   89 #define CAMSS_CSI_VFE0_CLK                              79
   90 #define CAMSS_CSI_VFE1_CLK                              80
   91 #define CAMSS_GP0_CLK                                   81
   92 #define CAMSS_GP1_CLK                                   82
   93 #define CAMSS_ISPIF_AHB_CLK                             83
   94 #define CAMSS_JPEG_DMA_CLK                              84
   95 #define CAMSS_JPEG_JPEG0_CLK                    85
   96 #define CAMSS_JPEG_JPEG1_CLK                    86
   97 #define CAMSS_JPEG_JPEG2_CLK                    87
   98 #define CAMSS_JPEG_JPEG_AHB_CLK                 88
   99 #define CAMSS_JPEG_JPEG_AXI_CLK                 89
  100 #define CAMSS_MCLK0_CLK                                 90
  101 #define CAMSS_MCLK1_CLK                                 91
  102 #define CAMSS_MCLK2_CLK                                 92
  103 #define CAMSS_MCLK3_CLK                                 93
  104 #define CAMSS_MICRO_AHB_CLK                             94
  105 #define CAMSS_PHY0_CSI0PHYTIMER_CLK             95
  106 #define CAMSS_PHY1_CSI1PHYTIMER_CLK             96
  107 #define CAMSS_PHY2_CSI2PHYTIMER_CLK             97
  108 #define CAMSS_TOP_AHB_CLK                               98
  109 #define CAMSS_VFE_VFE0_CLK                              99
  110 #define CAMSS_VFE_VFE1_CLK                              100
  111 #define CAMSS_VFE_VFE_AHB_CLK                   101
  112 #define CAMSS_VFE_VFE_AXI_CLK                   102
  113 #define FD_AXI_CLK                                              103
  114 #define FD_CORE_CLK                                             104
  115 #define FD_CORE_UAR_CLK                                 105
  116 #define MDSS_AXI_CLK                                    106
  117 #define MDSS_EXTPCLK_CLK                                107
  118 #define MDSS_HDMI_AHB_CLK                               108
  119 #define MDSS_HDMI_CLK                                   109
  120 #define MDSS_MDP_CLK                                    110
  121 #define MMSS_MISC_AHB_CLK                               111
  122 #define MMSS_MMSSNOC_AXI_CLK                    112
  123 #define MMSS_S0_AXI_CLK                                 113
  124 #define OCMEMCX_OCMEMNOC_CLK                    114
  125 #define OXILI_GFX3D_CLK                                 115
  126 #define OXILI_RBBMTIMER_CLK                             116
  127 #define OXILICX_AHB_CLK                                 117
  128 #define VENUS0_AHB_CLK                                  118
  129 #define VENUS0_AXI_CLK                                  119
  130 #define VENUS0_OCMEMNOC_CLK                             120
  131 #define VENUS0_VCODEC0_CLK                              121
  132 #define VENUS0_CORE0_VCODEC_CLK                 122
  133 #define VENUS0_CORE1_VCODEC_CLK                 123
  134 #define VENUS0_CORE2_VCODEC_CLK                 124
  135 #define AHB_CLK_SRC                                             125
  136 #define FD_AHB_CLK                                              126
  137 
  138 /* GDSCs */
  139 #define VENUS_GDSC                                              0
  140 #define VENUS_CORE0_GDSC                                1
  141 #define VENUS_CORE1_GDSC                                2
  142 #define VENUS_CORE2_GDSC                                3
  143 #define CAMSS_TOP_GDSC                                  4
  144 #define MDSS_GDSC                                               5
  145 #define JPEG_GDSC                                               6
  146 #define VFE_GDSC                                                7
  147 #define CPP_GDSC                                                8
  148 #define OXILI_GX_GDSC                                   9
  149 #define OXILI_CX_GDSC                                   10
  150 #define FD_GDSC                                                 11
  151 
  152 /* Resets */
  153 #define CAMSS_MICRO_BCR                                 0
  154 
  155 #endif

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