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     1 /* SPDX-License-Identifier: GPL-2.0+
    2  *
    3  * Copyright (C) 2020 Renesas Electronics Corp.
    4  */
    5 #ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
    6 #define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
    7 
    8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
    9 
   10 /* r8a7742 CPG Core Clocks */
   11 #define R8A7742_CLK_Z           0
   12 #define R8A7742_CLK_Z2          1
   13 #define R8A7742_CLK_ZG          2
   14 #define R8A7742_CLK_ZTR         3
   15 #define R8A7742_CLK_ZTRD2       4
   16 #define R8A7742_CLK_ZT          5
   17 #define R8A7742_CLK_ZX          6
   18 #define R8A7742_CLK_ZS          7
   19 #define R8A7742_CLK_HP          8
   20 #define R8A7742_CLK_B           9
   21 #define R8A7742_CLK_LB          10
   22 #define R8A7742_CLK_P           11
   23 #define R8A7742_CLK_CL          12
   24 #define R8A7742_CLK_M2          13
   25 #define R8A7742_CLK_ZB3         14
   26 #define R8A7742_CLK_ZB3D2       15
   27 #define R8A7742_CLK_DDR         16
   28 #define R8A7742_CLK_SDH         17
   29 #define R8A7742_CLK_SD0         18
   30 #define R8A7742_CLK_SD1         19
   31 #define R8A7742_CLK_SD2         20
   32 #define R8A7742_CLK_SD3         21
   33 #define R8A7742_CLK_MMC0        22
   34 #define R8A7742_CLK_MMC1        23
   35 #define R8A7742_CLK_MP          24
   36 #define R8A7742_CLK_QSPI        25
   37 #define R8A7742_CLK_CP          26
   38 #define R8A7742_CLK_RCAN        27
   39 #define R8A7742_CLK_R           28
   40 #define R8A7742_CLK_OSC         29
   41 
   42 #endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */
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