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     1 /* SPDX-License-Identifier: GPL-2.0+
    2  *
    3  * Copyright (C) 2015 Renesas Electronics Corp.
    4  */
    5 
    6 #ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
    7 #define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
    8 
    9 #include <dt-bindings/clock/renesas-cpg-mssr.h>
   10 
   11 /* r8a7793 CPG Core Clocks */
   12 #define R8A7793_CLK_Z                   0
   13 #define R8A7793_CLK_ZG                  1
   14 #define R8A7793_CLK_ZTR                 2
   15 #define R8A7793_CLK_ZTRD2               3
   16 #define R8A7793_CLK_ZT                  4
   17 #define R8A7793_CLK_ZX                  5
   18 #define R8A7793_CLK_ZS                  6
   19 #define R8A7793_CLK_HP                  7
   20 #define R8A7793_CLK_I                   8
   21 #define R8A7793_CLK_B                   9
   22 #define R8A7793_CLK_LB                  10
   23 #define R8A7793_CLK_P                   11
   24 #define R8A7793_CLK_CL                  12
   25 #define R8A7793_CLK_M2                  13
   26 #define R8A7793_CLK_ADSP                14
   27 #define R8A7793_CLK_ZB3                 15
   28 #define R8A7793_CLK_ZB3D2               16
   29 #define R8A7793_CLK_DDR                 17
   30 #define R8A7793_CLK_SDH                 18
   31 #define R8A7793_CLK_SD0                 19
   32 #define R8A7793_CLK_SD2                 20
   33 #define R8A7793_CLK_SD3                 21
   34 #define R8A7793_CLK_MMC0                22
   35 #define R8A7793_CLK_MP                  23
   36 #define R8A7793_CLK_SSP                 24
   37 #define R8A7793_CLK_SSPRS               25
   38 #define R8A7793_CLK_QSPI                26
   39 #define R8A7793_CLK_CP                  27
   40 #define R8A7793_CLK_RCAN                28
   41 #define R8A7793_CLK_R                   29
   42 #define R8A7793_CLK_OSC                 30
   43 
   44 #endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */
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