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     1 /* SPDX-License-Identifier: GPL-2.0+
    2  *
    3  * Copyright (C) 2015 Renesas Electronics Corp.
    4  */
    5 
    6 #ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
    7 #define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
    8 
    9 #include <dt-bindings/clock/renesas-cpg-mssr.h>
   10 
   11 /* r8a7794 CPG Core Clocks */
   12 #define R8A7794_CLK_Z2                  0
   13 #define R8A7794_CLK_ZG                  1
   14 #define R8A7794_CLK_ZTR                 2
   15 #define R8A7794_CLK_ZTRD2               3
   16 #define R8A7794_CLK_ZT                  4
   17 #define R8A7794_CLK_ZX                  5
   18 #define R8A7794_CLK_ZS                  6
   19 #define R8A7794_CLK_HP                  7
   20 #define R8A7794_CLK_I                   8
   21 #define R8A7794_CLK_B                   9
   22 #define R8A7794_CLK_LB                  10
   23 #define R8A7794_CLK_P                   11
   24 #define R8A7794_CLK_CL                  12
   25 #define R8A7794_CLK_CP                  13
   26 #define R8A7794_CLK_M2                  14
   27 #define R8A7794_CLK_ADSP                15
   28 #define R8A7794_CLK_ZB3                 16
   29 #define R8A7794_CLK_ZB3D2               17
   30 #define R8A7794_CLK_DDR                 18
   31 #define R8A7794_CLK_SDH                 19
   32 #define R8A7794_CLK_SD0                 20
   33 #define R8A7794_CLK_SD2                 21
   34 #define R8A7794_CLK_SD3                 22
   35 #define R8A7794_CLK_MMC0                23
   36 #define R8A7794_CLK_MP                  24
   37 #define R8A7794_CLK_QSPI                25
   38 #define R8A7794_CLK_CPEX                26
   39 #define R8A7794_CLK_RCAN                27
   40 #define R8A7794_CLK_R                   28
   41 #define R8A7794_CLK_OSC                 29
   42 
   43 #endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */
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