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     1 /* SPDX-License-Identifier: GPL-2.0 */
    2 /* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. */
    3 
    4 /*
    5  * This header provides constants for the nvidia,tegra241-gpio DT binding.
    6  *
    7  * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
    8  * provide names for this.
    9  *
   10  * The second cell contains standard flag values specified in gpio.h.
   11  */
   12 
   13 #ifndef _DT_BINDINGS_GPIO_TEGRA241_GPIO_H
   14 #define _DT_BINDINGS_GPIO_TEGRA241_GPIO_H
   15 
   16 #include <dt-bindings/gpio/gpio.h>
   17 
   18 /* GPIOs implemented by main GPIO controller */
   19 #define TEGRA241_MAIN_GPIO_PORT_A 0
   20 #define TEGRA241_MAIN_GPIO_PORT_B 1
   21 #define TEGRA241_MAIN_GPIO_PORT_C 2
   22 #define TEGRA241_MAIN_GPIO_PORT_D 3
   23 #define TEGRA241_MAIN_GPIO_PORT_E 4
   24 #define TEGRA241_MAIN_GPIO_PORT_F 5
   25 #define TEGRA241_MAIN_GPIO_PORT_G 6
   26 #define TEGRA241_MAIN_GPIO_PORT_H 7
   27 #define TEGRA241_MAIN_GPIO_PORT_I 8
   28 #define TEGRA241_MAIN_GPIO_PORT_J 9
   29 #define TEGRA241_MAIN_GPIO_PORT_K 10
   30 #define TEGRA241_MAIN_GPIO_PORT_L 11
   31 
   32 #define TEGRA241_MAIN_GPIO(port, offset) \
   33         ((TEGRA241_MAIN_GPIO_PORT_##port * 8) + (offset))
   34 
   35 /* GPIOs implemented by AON GPIO controller */
   36 #define TEGRA241_AON_GPIO_PORT_AA 0
   37 #define TEGRA241_AON_GPIO_PORT_BB 1
   38 
   39 #define TEGRA241_AON_GPIO(port, offset) \
   40         ((TEGRA241_AON_GPIO_PORT_##port * 8) + (offset))
   41 
   42 #endif
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