1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * MIO pin configuration defines for Xilinx Zynq
4 *
5 * Copyright (C) 2021 Xilinx, Inc.
6 */
7
8 #ifndef _DT_BINDINGS_PINCTRL_ZYNQ_H
9 #define _DT_BINDINGS_PINCTRL_ZYNQ_H
10
11 /* Configuration options for different power supplies */
12 #define IO_STANDARD_LVCMOS18 1
13 #define IO_STANDARD_LVCMOS25 2
14 #define IO_STANDARD_LVCMOS33 3
15 #define IO_STANDARD_HSTL 4
16
17 #endif /* _DT_BINDINGS_PINCTRL_ZYNQ_H */
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