Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/include/dt-bindings/pinctrl/rzn1-pinctrl.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Defines macros and constants for Renesas RZ/N1 pin controller pin 4 * muxing functions. 5 */ 6 #ifndef __DT_BINDINGS_RZN1_PINCTRL_H 7 #define __DT_BINDINGS_RZN1_PINCTRL_H 8 9 #define RZN1_PINMUX(_gpio, _func) \ 10 (((_func) << 8) | (_gpio)) 11 12 /* 13 * Given the different levels of muxing on the SoC, it was decided to 14 * 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO 15 * muxes are all represented by one single value. 16 * 17 * You can derive the hardware value pretty easily too, as 18 * 0...9 are Level 1 19 * 10...71 are Level 2. The Level 2 mux will be set to this 20 * value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be 21 * set accordingly. 22 * 72...103 are for the 2 MDIO muxes. 23 */ 24 #define RZN1_FUNC_HIGHZ 0 25 #define RZN1_FUNC_0L 1 26 #define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2 27 #define RZN1_FUNC_CLK_ETH_NAND 3 28 #define RZN1_FUNC_QSPI 4 29 #define RZN1_FUNC_SDIO 5 30 #define RZN1_FUNC_LCD 6 31 #define RZN1_FUNC_LCD_E 7 32 #define RZN1_FUNC_MSEBIM 8 33 #define RZN1_FUNC_MSEBIS 9 34 #define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */ 35 36 #define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0) 37 #define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1) 38 #define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2) 39 #define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3) 40 #define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4) 41 #define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5) 42 #define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6) 43 #define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7) 44 #define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8) 45 #define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9) 46 #define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10) 47 #define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11) 48 #define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12) 49 #define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13) 50 #define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14) 51 #define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15) 52 #define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16) 53 #define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17) 54 #define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18) 55 #define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19) 56 #define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20) 57 #define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21) 58 #define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22) 59 #define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23) 60 #define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24) 61 #define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25) 62 #define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26) 63 #define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27) 64 #define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28) 65 #define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29) 66 #define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30) 67 #define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31) 68 #define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32) 69 #define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33) 70 #define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34) 71 #define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35) 72 #define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36) 73 #define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37) 74 #define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38) 75 #define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39) 76 #define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40) 77 #define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41) 78 #define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42) 79 #define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43) 80 #define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44) 81 #define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45) 82 #define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46) 83 #define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47) 84 #define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48) 85 #define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49) 86 #define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50) 87 #define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51) 88 #define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52) 89 #define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53) 90 #define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54) 91 #define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55) 92 #define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56) 93 #define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57) 94 #define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58) 95 #define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59) 96 #define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60) 97 #define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61) 98 99 #define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62) 100 101 /* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */ 102 #define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0) 103 #define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1) 104 #define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2) 105 #define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3) 106 #define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4) 107 #define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5) 108 #define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6) 109 #define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7) 110 /* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ 111 #define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8) 112 #define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9) 113 #define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10) 114 #define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11) 115 #define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12) 116 #define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13) 117 #define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14) 118 #define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15) 119 120 /* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */ 121 #define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16) 122 #define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17) 123 #define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18) 124 #define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19) 125 #define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20) 126 #define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21) 127 #define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22) 128 #define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23) 129 /* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ 130 #define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24) 131 #define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25) 132 #define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26) 133 #define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27) 134 #define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28) 135 #define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29) 136 #define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30) 137 #define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31) 138 139 #define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32) 140 141 #endif /* __DT_BINDINGS_RZN1_PINCTRL_H */
Cache object: 66aeadba10cc001859aa54efbfe22e38
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]